PROACTIVE: Computer-aided Testing, Verification, and Power Management Research

The publications are listed under the following Research Areas:

• Architectural-level and gate-level automatic test pattern generation (ATPG)
• Design verification and diagnosis
• Design for testability (DFT)
• Test set compaction
• Fault simulation and defect coverage evaluation
• Power estimation and management in VLSI
• Computer architecture
• Security, Parallelization and Reliability.

Architectural-level and gate-level test generation

This research is supported in part by:
NSF, SRC, NJCST, Intel, Fujitsu.

• "RTL test generation on multi-core and many-core architectures,"
  Aravind Krishnan Varadarajan and Michael S. Hsiao,
  in Proceedings of the International Conference on VLSI Design, Jan. 2019.
• "Fast search-based RTL test generation using control-flow path guidance,"
  Sonal Pinto and Michael S. Hsiao,
  in Proceedings of the International Conference on Computer Design, Nov. 2017.
• "RTL Functional Test Generation Using Factored Concolic Execution,"
  Sonal Pinto and Michael S. Hsiao,
  in Proceedings of the International Test Conference, Oct. 2017.
• "Reachability analysis in RTL circuits using k-induction bounded model checking,"
  Tonmoy Roy and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, October, 2017.
• "A test pattern quality metric for diagnosis of multiple stuck-at and transition faults,"
  Sarmad Tanwir, Michael S. Hsiao, and Loganathan Lingappan,
  in Proceedings of the ACM Great Lakes Symposium on VLSI, May 2017.
• "A framework for fast test generation at the RTL,"
  Kelson Gent, Akash Agrawal, and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Test Symposium, April 2017.
• "Hardware-in-the-loop model-less diagnostic test generation,"
  Sarmad Tanwir, Michael S. Hsiao, and Loganathan Lingappan,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, October, 2016.
• "Fast multi-level test generation at the RTL,"
  Kelson Gent and Michael S. Hsiao,
  in Proceedings of the IEEE Annual Symposium on VLSI, July 2016.
• "A control path aware metric for grading functional test vectors,"
  Kelson Gent and Michael S. Hsiao,
  in Proceedings of the IEEE Latin American Test Symposium, April 2016.
• "Dynamic partitioning strategy to enhance symbolic execution,"
  Brendan Marcellino and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europei Conf., March 2016.
• "SI-SMART: functional test generation for RTL circuits using loop abstraction and learning recurrence relationships,"
  Prateek Puri and Michael S. Hsiao,
  in Proceedings of the IEEE International Conference on Computer Design, October 2015.
• "Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution,"
  Prateek Puri,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, August 2015.
• "Fast stimuli generation for design validation of RTL circuits using binary particle swarm optimization,"
  Prateek Puri and Michael S. Hsiao,
  in Proceedings of the IEEE International Sympoisum on VLSI, July 2015.
• "Branch guided functional test generation at the RTL,"
  Vineeth Acharya, Sharad Bagri, and Michael S. Hsiao,
  in Proceedings of the IEEE European Test Symposium, May 2015.
• "Abstraction-based relation mining for functional test generation,"
  Kelson Gent and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Test Symposium, May 2015.
• "Signal domain based reachability analysis in RTL circuits,"
  Sharad Bagri, Kelson Gent, and Michael S. Hsiao,
  in Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2015.
• "Fast static learning and inductive reasoning with application to untestable fault identification,"
  Michael Dsouza,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, March 2015.
• "Branch Guided Metrics for Functional and Gate-level Testing,"
  Vineeth Acharya,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, March 2015.
• "Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution,"
  Sharad Bagri,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, March 2015.
• "Strategies for Quality and Performance Improvement of Hardware Verification and Synthesis Algorithms,"
  Mahmoud Elbayoumi,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2014.
• "Techniques for Enhancing Test and Diagnosis of Digital Circuits,"
  Sarvesh Prabhu,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2014.
• "Dual-purpose mixed-level test generation using swarm intelligence",
  Kelson Gent and Michael S. Hsiao,
  in Proceedings of the IEEE Asian Test Symposium, November 2014.
• "Test generation for circuits with embedded memories using SMT,"
  Sarvesh Prabhu and Michael S. Hsiao,
  in Proceedings of the IEEE European Test Symposium, May 2013.
• "Launch-on-shift test generation for testing scan designs containing synchronous and asynchronous clock domains,"
  Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang,
  in ACM Trans. Design Automation of Electronic Systems, vol. 17, no. 4, 2012.
• "Design validation of RTL circuits using evolutionary swarm intelligence,"
  Min Li, Kelson Gent, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, November, 2012.
• "Acceleration of hardware testing and validation algorithms using graphics processing units,"
  Min Li,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2012.
• "A SMT-based diagnostic test generation method for combinational circuits,"
  Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan and Vijay Gangaram,
  in Proceedings of the IEEE VLSI Test Symposium, April 2012, pp. 215-220.
• "An efficient 2-phase strategy to achieve high branch coverage,"
  Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram and Jim Grundy,
  in Proceedings of the IEEE Asian Test Symposium, November 2011.
• "Strategies for scalable symbolic execution-driven test generation for programs,"
  Saparya Krishnamoorthy, Michael S. Hsiao, and Loganathan Lingappan,
  in Science China Information Sciences, vol. 54, no. 9, pp. 1797-1812, 2011.
• "Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains,"
  Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, and Lizhen Yu,
  in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 3, March, 2011, pp. 455-463.
• "A novel learning framework for state space exploration based on search state extensibility relation," (pdf)
  Maheshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Design Conference, January 2011, pp. 64-69.
• "Fault collapsing using a novel extensibility relation," (pdf)
  Maheshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Design Conference, January 2011, pp. 268-273.
• "Testing and verifiation strategies for enhancing trust in third party IPs,"
  Mainak Banga,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2010.
• "Tackling the path explosion problem in symbolic execution-driven test generation," (pdf)
  Saparya Krishnamoorthy, Michael S. Hsiao, and Loganathan Lingappan,
  in Proceedings of the IEEE Asian Test Symposium, December 2010, pp. 59-64.
• "Search State Extensibility-based Learning for Model Checking and Test Generation,"
  Maheshwar Chandrasekar,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2010.
• "Strategies for Scalable Symbolic Execution-based Test Generation,"
  Saparya Krishnamoorthy,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, July 2010.
• "Trusted RTL: Trojan detection methodology in pre-silicon designs," (pdf)
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the IEEE Hardware-Oriented Security and Trust Symposium, June 2010, pp. 56-59.
• "An ant colony optimization technique for abstraction-guided state justification,"
  Min Li and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, November 2009.
• "Fault Simulation and Test Generation,"
  James C.-M. Li and Michael S. Hsiao,
  book chapter in Electronic Design Automation: Synthesis, Verification, and Test, edited by Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Cheng, Morgan Kaufmann, San Francisco, CA, pp. 851-917, 2009.
• "A novel sustained vector technique for the detection of hardware trojans,"
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the IEEE International VLSI Design Conf., January, 2009, pp. 327-332.
• "SAT-based state justification with adaptive mining of invariants,"(pdf)
  Weixin Wu and Michael S. Hsiao,
  in International Test Conf., October 2008.
• "On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs," (pdf)
  Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James C.-M. Li, Jiun-Lang Huang, and Ravi Apte,
  in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 143-151, October, 2008.
• "Partition based Approaches for the Isolation and Detection of Embedded Trojans in ICs,"
  Mainak Banga,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2008.
• "A region based approach for the identification of hardware trojans," (pdf)
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the Hardware-Oriented Security and Trust Workshop, pp. 40-47, June 2008.
• "Bilateral testing of nano-scale fault-tolerant circuits," (pdf)
  Lei Fang and Michael S. Hsiao,
  Journal of Electronic Testing: Theory and Applications, vol. 24, no. 1-3, June 2008, pp. 285-296.
• "Guided test generation for isolation and detection of embedded trojans in ICs," (pdf)
  Mainak Banga, Maheshwar Chandrasekar, Lei Fang, and Michael S. Hsiao,
  in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, April 2008, pp. 363-366.
• "Efficient design validation based on cultural algorithms," (pdf)
  Weixin Wu and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2008, pp. 402-407.
• "Delay Testing,"
  Duncan M. Walker and Michael S. Hsiao,
  book chapter in System-on-Chip Test Architectures, edited by Laung-Terng Wang, Charles E. Stroud, and Nur A. Touba, Morgan Kaufmann, San Francisco, CA, pp. 263-306, 2007.
• "Mining-guided state justification with partitioned navigation tracks," (pdf)
  Ankur Parikh, Weixin Wu, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, Oct. 2007.
• "Efficient power droop aware delay fault testing," (pdf)
  Bin Li, Lei Fang, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, Oct. 2007.
• "Mining sequential constraints for pseudo-functional testing," (pdf)
  Weixin Wu and Michael S. Hsiao,
  in Proceedings of the IEEE Asian Test Symposium, Oct., 2007, pp. 19-24.
• "Mining-guided sequential ATPG with partitioned navigation tracks for design validation,"
  Weixin Wu and Michael S. Hsiao,
  in TECHCON, September 2007.
• "Efficient search space pruning for multi valued SAT based ATPG,"
  Maheshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE European Test Symposium, May, 2007.
• "A new hybrid solution to boost SAT solver performance," (pdf)
  Lei Fang and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2007, pp. 1307-1313.
• "A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage," (pdf)
  Liang Zhang, Indradeep Ghosh, and Michael S. Hsiao,
  in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, November 2006, pp. 2526-2538.
• "Simulation-based internal variable range coverage metric and test generation model,"
  Xueqi Cheng and Michael S. Hsiao,
  in Proceedings of the International Conf. on Software Engineering and Applications, November 2006, pp. 352-357.
• "State variable extraction and partitioning to reduce problem complexity for ATPG and design validation," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  in the IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, Oct. 2006, pp. 2275-2282.
• "Characteristic states & cooperative game based search for efficient sequential ATPG and design validation," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conf., paper 24.2, October 2006.
• "A study of implication based pseudo functional testing," (pdf)
  Manan Syal, Kameshwar Chandrasekar , Vishnu Vimjam, Michael S. Hsiao, Yi-Shing Chang, and Sreejit Chakravarty,
  in Proceedings of the IEEE International Test Conf., paper 24.3, October 2006.
• "Bilateral testing of nano-scale fault-tolerant circuits," (pdf)
  Lei Fang and Michael S. Hsiao,
  in Proceedings of the IEEE Defect and Fault Tolerance Conf., October 2006, pp. 309-317.
• "A complete & practical approach to ensure the legality of a signal transmitted by a cognitive radio,"
  Patrick Cowhig,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2006.
• "Test Generation,"
  Michael S. Hsiao,
  book chapter in VLSI Test Principles and Architectures, edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, Morgan Kaufmann, San Francisco, CA, pp. 161-262, 2006.
• "New techniques for untestable fault identification in sequential circuits," (pdf)
  Manan Syal and Michael S. Hsiao,
  in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 6, pp. 1117-1131, June, 2006.
• "Exploring temporal & spatial correlations on circuit variables for enhancing simulation-based test generation,"
  Xiaoding Chen,
  Ph.D. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, June 2006.
• "Efficient fault collapsing via generalized dominance relations," (pdf)
  Vishnu Vimjam and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Test Sympium, April 2006, pp. 258-263.
• "Search-space aware learning technqiues for unbounded model checking and path delay testing,"
  Kameshwar Chandrasekar ,
  Ph.D Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, April 2006.
• "A new fault model and test generation framework for nanoscale fault-tolerant circuits,"
  Lei Fang and Michael S. Hsiao,
  Technical Report 2006-02-1, PROACTIVE Lab, Virginia Tech, February, 2006.
• "Testing embedded sequential cores in parallel using spectrum-based BIST," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  in the IEEE Transactions on Computers, vol. 55, no. 2, pp. 150-162, February 2006.
• "Untestable multi-cycle path delay faults in industrial designs," (pdf)
  Manan Syal, Suriyaprakash Natarajan, Sreejit Chakravarty, and Michael S. Hsiao,
  in Proceedings of the IEEE Asian Test Symp., December 2005, pp. 194-201.
• "A novel transition fault ATPG that reduces yield loss," (pdf)
  Xiao Liu and Michael S. Hsiao,
  in the IEEE Design & Test of Computers, vol. 22, no. 6, pp. 576-584, November-December, 2005.
• "Extended forward implications and dual recurrence relations to identify sequentially untestable faults," (pdf) Manan Syal, Rajat Arora, and Michael S. Hsiao,
  in Proceedings of the IEEE International Conference on Computer Design, October 2005, pp. 453-460.
• "Static learning for problems in VLSI test and verification,"
  Manan Syal ,
  Ph.D Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, June 2005.
• "Efficient techniques for transition testing," (pdf)
  Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, and Paul J. Thadikaran,
  in the ACM Transactions on Design Automation of Electronic Systems, vol. 10, no. 2, pp. 258-278, April 2005.
• "Forward image computation with backtracing ATPG and incremental state-set construction," (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, April 2005, pp. 254-259.
• "An effective and efficient ATPG-based combinational equivalence checker," (pdf)
  Ronald P. Lajaunie and Michael S. Hsiao,
  in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, April 2005, pp. 248-253.
• "Untestable fault identification through enhanced necessary value assignments," (pdf)
  Vishnu C. Vimjam, Manan Syal, and Michael S. Hsiao,
  in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, April 2005, pp. 176-181.
• "Integration of learning techniques into incremental satisfiability for efficient path-delay fault test generation," (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2005, pp. 1002-1007.
• "Design verification for sequential systems at various abstraction levels,"
  Liang Zhang,
  Ph.D Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, January 2005.
• "Success-driven learning in ATPG for preimage computation," (pdf)
  Shuo Sheng and Michael S. Hsiao,
  in the IEEE Design & Test of Computers, vol. 21, no. 6, pp. 504-512, November-December 2004.
• "On identifying functionally untestable transition faults," (pdf)
  Xiao Liu and Michael S. Hsiao,
  in Proceedings of the IEEE High-Level Design Validation and Test Workshop, November 2004, pp. 121-126.
• "CNF formula simplification using implication reasoning," (pdf)
  Rajat Arora and Michael S. Hsiao,
  in Proceedings of the IEEE High-Level Design Validation and Test Workshop, November 2004, pp. 129-134.
• "Decision selection and learning for an 'all solutions ATPG engine', " (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, October 2004, pp. 607-616.
• "State variable extraction to reduce problem complexity for ATPG and design validation," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, October 2004, pp. 820-829.
• "ALAPTF: A new transition fault model and the ATPG algorithm," (pdf)
  Puneet Gupta and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, October 2004, pp. 1053-1060.
• "Identifying untestable transition faults in latch based designs with multiple clocks," (pdf)
  Manan Syal, Sreejit Chakravarty, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, October 2004, pp. 1034-1043.
• "ATPG and DFT algorithms for delay fault testing,"
  Xiao Liu,
  Ph.D. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, July 2004.
• "Efficient ATPG for design validation based on partitioned state exploration histories," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Test Symposium, April 2004, pp. 389-394.
• "ALAPT: A new transition fault model for small delay faults,"
  Puneet Gupta and Michael S. Hsiao,
  International Test Synthesis Workshop, March 2004.
• "High quality transition and small delay fault ATPG,"
  Puneet Gupta,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, January 2004.
• "Untestable fault identification using recurrence relations and impossible value assignments," (pdf)
  Manan Syal and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Design Conference, January, 2004, pp. 481-486.
• "Can SAT be used to improve sequential ATPG methods?" (pdf)
  Mukul R. Prasad, Michael S. Hsiao, and Jawahar Jain,
  in Proceedings of the IEEE VLSI Design Conference, January, 2004, pp. 585-590.
• "Automatic design validation framework for HDL description via RTL ATPG," (pdf)
  Liang Zhang, Michael S. Hsiao, and Indradeep Ghosh,
  Proceedings of the IEEE Asian Test Symposium, November 2003, pp. 148-153.
• "ATPG-based preImage computation: efficient search space pruning with ZBDD," (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  Proceedings of the IEEE High-Level Design Validation and Test Workshop, November 2003, pp. 117-122.
• "Constrained ATPG for broadside transition testing," (pdf)
  Xiao Liu and Michael S. Hsiao,
  in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2003, pp. 175-182.
• "Efficient sequential ATPG based on partitioned finite-state-machine traversal," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  Proceedings of the IEEE International Test Conference, September, 2003, pp. 281-289.
• "Efficient sequential ATPG for functional RTL circuits," (pdf)
  Liang Zhang, Indradeep Ghosh, and Michael S. Hsiao,
  Proceedings of the IEEE International Test Conference, September, 2003, pp. 290-298.
• "High quality ATPG for delay defects," (pdf)
  Puneet Gupta and Michael S. Hsiao,
  Proceedings of the IEEE International Test Conference, September, 2003, pp. 584-591.
• "Efficient transition fault ATPG algorithms based on stuck-at test vectors," (pdf)
  Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, and Paul J. Thadikaran,
  in the Journal of Electronic Testing Theory and Applications, vol. 19, no. 4, pp. 437-445, August, 2003.
• "ATPG based preimage computation: efficient search space pruning using ZBDD,"
  Kameshwar Chandrasekar,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, July 2003.
• "Testing and verification by exploring circuit properties,"
  Shuo Sheng,
  Ph.D. Dissertation, Department of Electrical and Computer Engineering, Rutgers University, July 2003.
• "A novel ATPG for formal verification,"
  Shuo Sheng and Michael S. Hsiao,
  Proceedings of the IEEE Microprocessor Test and Verification Workshop, May 2003.
• "Efficient implication-based untestable bridge fault identifier," (pdf)
  Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, and Sreejit Chakravarty,
  Proceedings of the IEEE VLSI Test Symposium, April 2003, pp. 393-398.
• "High quality delay testing,"
  Puneet Gupta and Michael S. Hsiao,
  Proceedings of the IEEE Concurrent and Defect-Based Testing Workshop, April 2003.
• "Efficient preimage computation using a novel success-driven ATPG," (pdf)
  Shuo Sheng and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2003, pp. 822-827.
• "High-level automatic test generation for design verification,"
  Liang Zhang, Michael S. Hsiao, and Indradeep Ghosh,
  10th IEEE International Test Synthesis Workshop, March, 2003.
• "A novel, low-cost algorithm for sequentially untestable fault identification," (pdf)
  Manan Syal and Michael S. Hsiao,
  Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2003, pp. 316-321.
• "Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors"
  Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, and Paul J. Thadikaran
  in the Journal of Electronic Testing: Theory and Applications, vol. 19, no. 4, pp. 437-445, August, 2003.
• "Untestable fault identification using implications,"
  Manan Syal,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2002.
• "Characteristic faults and spectral information for logic BIST," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  Proceedings of the IEEE International Conference on Computer-Aided Design, November 2002, pp. 294-298.
• "Techniques to reduce data volume and application time for transition test,'' (pdf)
  Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, and Paul J. Thadikaran,
  Proceedings of the IEEE International Test Conference, October 2002, pp. 983-992..
• "Efficient sequential test generation based on logic simulation," (pdf)
  Shuo Sheng and Michael S. Hsiao,
  in the IEEE Design and Test of Computers, vol. 19, no. 5, pp. 56-64, September-October, 2002.
• "Effective safety property checking using simulation-based ATPG," (pdf)
  Shuo Sheng, Koichiro Takayama, and Michael S. Hsiao,
  Proceedings of the IEEE Design Automation Conference, June 2002, pp. 813-818.
• "Improving sequential ATPG using SAT methods,"
  Mukul R. Prasad, Michael S. Hsiao, and Jawahar Jain,
  Proceedings of the IEEE/ACM International Workshop on Logic & Synthesis,June 2002.
• "Novel ATPG Algorithm for Transition Faults," (pdf)
  Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, and Paul J. Thadikaran,
  Proceedings of the IEEE European Test Workshop, May, 2002.
• "Spectrum-based BIST in complex SOCs," (pdf)
  Ganapathy Kasturirangan and Michael S. Hsiao,
  Proceedings of the IEEE VLSI Test Symposium, April 2002, pp. 111-116.
• "Maximizing impossibilities for untestable fault identification," (pdf) Michael S. Hsiao,
  Proceedings of the IEEE Design Automation and Test in Europe Conference, March, 2002, pp. 949-953.
• "State and fault information for compaction-based test generation," (pdf)
  Ashish Giani, Shuo Sheng, Michael S. Hsiao, and Vishwani Agrawal,
  in the Journal of Electronic Testing: Theory and Applications, vol. 18, no. 1, pp. 63-72, February, 2002.
• "Spectral Analysis for Automatic Test Pattern Generation,"
  Ganapathy Kasturirangan,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, July, 2001.
• "Study of relationship between high level and logic level vector sets,"
  Aaresh Powvalla, Ganapathy Kasturirangan, Liang Zhang, and Michael S. Hsiao,
  in the 10th IEEE North Atlantic Test Workshop, May, 2001.
• "Novel spectral methods for built-in self-test in a system-on-a-chip environment," (pdf)
  Ashish Giani, Shuo Sheng, Michael S. Hsiao, and Vishwani Agrawal,
  Proceedings of the IEEE VLSI Test Symposium,, April, 2001, pp. 163-168.
• "Efficient spectral techniques for sequential ATPG," (pdf)
  Ashish Giani, Shuo Sheng, Michael S. Hsiao, and Vishwani Agrawal,
  Proceedings of the IEEE Design Automation and Test in Europe Conference, March, 2001, pp. 204-208.
• "Embedded core testing using genetic algorithms,"
  Ruofan Xu and Michael S. Hsiao,
  in TAPTechnology, second Edition, pp. 19-25, 2001.
• "Compaction-based test generation using state and fault information," (pdf)
  Ashish Giani, Shuo Sheng, Michael S. Hsiao, and Vishwani Agrawal,
  Proceedings of the IEEE Asian Test Symposium, December, 2000, pp. 159-164.
• "Embedded core testing using genetic algorithms," (pdf)
  Ruofan Xu and Michael S. Hsiao,
  Proceedings of the IEEE Asian Test Symposium, December, 2000, pp. 254-259.
• "Dynamic state traversal for sequential circuit test generation," (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in the ACM Transactions on Design Automation of Electronic Systems, vol. 5, no. 3, pp. 548-565, July 2000.
• "Testing, verification, and diagnosis in the presence of unknowns,"
  Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao,
  in TAPTechnology, Launch Edition, pp. 27-33, July, 2000.
• "Testability evaluation and test generation for system-on-a-chip,"
  Ruofan Xu,
  M.S. Thesis , Department of Electrical and Computer Engineering, Rutgers University, July 2000.
• "Study of compaction-based ATPG for sequential circuits,"
  Ashish Giani,
  M.S. Thesis , Department of Electrical and Computer Engineering, Rutgers University, June 2000.
• "Correlation-based test generation for sequential circuits,"
  Ashish Giani, Shuo Sheng, Michael S. Hsiao, and Vishwani Agrawal,
  in 9th IEEE North Atlantic Test Workshop, May, 2000, pp. 76-83.
• "Testing, verification, and diagnosis in the presence of unknowns," (pdf)
  Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Michael S. Hsiao, Masahiro Fujita,
  Proceedings of The IEEE VLSI Test Symposium, April, 2000, pp. 263-269.
• "Multi-node static logic implications for redundancy identification," (pdf)
  Kabir Gulrajani and Michael S. Hsiao,
  Proceedings of The IEEE Design, Automation, and Test in Europe Conference, Mar., 2000, pp. 729-733.
• "Evaluation for controllability and observability of embedded cores in SOC,"
  Ruofan Xu and Michael S. Hsiao,
  in 7th IEEE International Test Synthesis Workshop, March, 2000.
• "Correlation analysis of compacted test vectors and the use of correlated vectors for test generation,"
  Shuo Sheng, Ankur Jain, Michael S. Hsiao, and Vishwani Agrawal,
  in 7th IEEE International Test Synthesis Workshop, March, 2000.
• "Multi-node implications for sequential circuit reachability analysis and redundancy identification,"
  Kabir Gulrajani,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, July 1999.
• "On using static compaction for weighted random test patterns,"
  Ankur Jain, Vishwani Agrawal, and Michael S. Hsiao,
  6th IEEE International Test Synthesis Workship, March, 1999.
• "Multi-node static logic implications for redundancy identification,"
  Kabir Gulrajani and Michael S. Hsiao,
  6th IEEE International Test Synthesis Workship, March, 1999.
• "Application of genetically-engineered finite-state-machine sequences to sequential circuit ATPG" (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 239-254, March 1998.
• "Sequential circuit test generation using genetic techniques," (pdf)
  Michael S. Hsiao,
  Ph. D. Dissertation, Department of Electrical and Computer Engineering, Tech. Report CRHC-97-09/UILU-ENG-97-2213, University of Illinois, May, 1997
• "Sequential circuit test generation using dynamic state traversal," (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in Proceedings of the IEEE European Design and Test Conference, Mar., 1997, pp. 22-28.
• "A genetic-algorithm approach to architectural-level justification of precomputed vectors,"
  Michael S. Hsiao, and Janak H. Patel,
  Coordinated Science Laboratory, University of Illinois, Urbana, IL, Technical Report CRHC-96-2221/UILU-ENG-96-11, Sep., 1996.
• "Automatic test generation using genetically-engineered distinguishing sequences" (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in Proceedings of the IEEE VLSI Test Symposium, Apr., 1996, pp. 216-223.
• "Alternating strategies for sequential circuit ATPG" (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  Proceedings of the IEEE European Design and Test Conference, Mar., 1996, pp. 368-374.

Design for testability (DFT)

This research is supported in part by:
NSF, NJCST, Intel, Fujitsu.

• "A diagnosis-friendly LBIST architecture with property checking",
  Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, October 2014.
• "LFSR seed computation and reduction using SMT-based fault-chaining,"
  Dhrumeel Bakshi and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March, 2013.
• "LBIST Reseeding With a New SMT-based Chainability Analysis,"
  Dhrumeel Bakshi, Sarvesh Prabhu, and Michael S. Hsiao,
  in SRC TECHCON, September 2012.
• "Techniques for seed computation and testability enhancement for logic Built-In Self Test,"
  Dhrumeel Bakshi,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2012.
• "Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers,"
  Supratik Misra,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, February 2012.
• "A novel SMT-based technique for LFSR reseeding,"
  Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan and Vijay Gangaram,
  in Proceedings of the IEEE VLSI Design Conference, January 2012.
• "Architectures for testing 3D chips using time-division demultiplexing/multiplexing,"
  Laung-Terng Wang, Nur A. Touba, Michael S. Hsiao, Jiun-Lang Huang, James Chien-Mo Li, Shianling Wu, Xiaoqing Wen, Manish Bhattaraie, Fangfang Li, and Zhigang Jiang,
  in Proceedings of the IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, September 2011.
• "ODETTE: A Non-Scan Design-for-Test Methodology for Trojan Detection in ICs,"
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the IEEE Hardware-Oriented Security and Trust Symposium, June 2011.
• "Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains,"
  Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, and Lizhen Yu,
  in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 3, March, 2011, pp. 455-463.
• "Design-for-test methodology for non-scan at-speed testing,"
  Mainak Banga, Nikhil Rahagude, and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2011.
• "Integrated enhancement of testability and diagnosability for digital circuits,"
  Nikhil Rahagude,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, November 2010.
• "Sharing of logic and test TSVs for testing of 3DICs,"
  Shravan Garlapati, Michael S. Hsiao, and Leyla Nazhandali,
  in Proceedings of the IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, November 2010.
• "DFT + DFD: an integrated method for design for testability and diagnosability," (pdf)
  Nikhil Rahagude, Maheshwar Chandrasekar, and Michael S. Hsiao,
  in Proceedings of the IEEE Asian Test Symposium, December 2010, pp. 218-223.
• "Using non-trivial logic implications for trace buffer-based silicon debug," (pdf)
  Sandesh Prabhakar and Michael S. Hsiao,
  in Proceedings of the IEEE Asian Test Symposium, November 2009, pp. 131-136.
• "Kiss the scan goodbye: a non-scan architecture for high coverage, low test data volume and low test application time,"
  Michael S. Hsiao and Mainak Banga,
  in Proceedings of the IEEE Asian Test Symposium, November 2009, pp. 225-230.
• "Fast circuit topology based method to configure the scan chains in Illinois scan architecture,"
  Swapneel Donglikar, Mainak Banga, Maheshwar Chandrasekar, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, November 2009.
• "DFT Techniques to Optimize VLSI Test Cost,"
  Swapneel Donglikar,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, June 2009.
• "A new scan architecture for both low power testing and test volume compression under SOC test environment," (pdf)
  Hong-Sik Kim, Sungho Kang and Michael S. Hsiao,
  Journal of Electronic Testing: Theory and Applications, vol. 24, no. 4, August 2008, pp. 365-378.
• "On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs,"
  Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James C.-M. Li, Jiun-Lang Huang, and Ravi Apte,
  in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 143-151, October, 2008.
• "An overlapping scan architecture for reducing both test time & test power by pipelining fault detection," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  in IEEE Transactions on VLSI Systems, vol. 15, no. 4, April 2007, pp. 404-412.
• "Testing embedded sequential cores in parallel using spectrum-based BIST," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  in the IEEE Transactions on Computers, vol. 55, no. 2, pp. 150-162, February 2006.
• "Reduce testing time by partitioning the scan flops and pipelining excitation and propagation of different fault sets,"
  Xiaoding Chen and Michael S. Hsiao,
  in IEEE International Test Synthesis Workshop, April 2005.
• "ATPG and DFT algorithms for delay fault testing,"
  Xiao Liu,
  Ph.D. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, July 2004.
• "Energy-efficient logic BIST based on state correlation analysis," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  Proceedings of the IEEE VLSI Test Symposium, April 2003, pp. 267-272.
• "Experimental study of scan based transition fault testing techniques,"
  Vinay Jayaram,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, January 2003.
• "Behavioral-level DFT via formal operator testability measures," (pdf)
  Sandhya Seshadri and Michael S. Hsiao
  in the Journal of Electronic Testing Theory and Applications, vol. 18, no. 6, pp. 595-611, December, 2002.
• "Characteristic faults and spectral information for logic BIST," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  Proceedings of the IEEE International Conference on Computer-Aided Design, November 2002, pp. 294-298.
• "Techniques to reduce data volume and application time for transition test,'' (pdf)
  Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, and Paul J. Thadikaran,
  Proceedings of the IEEE International Test Conference, October 2002, pp. 983-992.
• "Novel ATPG Algorithm for Transition Faults," (pdf)
  Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, and Paul J. Thadikaran,
  Proceedings of the IEEE European Test Workshop, May, 2002.
• "Spectrum-based BIST in complex SOCs," (pdf)
  Ganapathy Kasturirangan and Michael S. Hsiao,
  Proceedings of the IEEE VLSI Test Symposium, April 2002, pp. 111-116.
• "Spectral Analysis for Automatic Test Pattern Generation,"
  Ganapathy Kasturirangan,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, July, 2001.
• "SOC-friendly testing of embedded cores,"
  Aaresh Powvalla,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, July, 2001.
• "Novel spectral methods for built-in self-test in a system-on-a-chip environment," (pdf)
  Ashish Giani, Shuo Sheng, Michael S. Hsiao, and Vishwani Agrawal,
  Proceedings of the IEEE VLSI Test Symposium,, April, 2001, pp. 163-168.
• "Embedded core testing using genetic algorithms,"
  Ruofan Xu and Michael S. Hsiao,
  in TAPTechnology, second Edition, pp. 19-25, 2001.
• "Combination of structural and state analysis for partial scan," (pdf)
  Sameer Sharma and Michael S. Hsiao,
  Proceedings of the IEEE VLSI Design Conference, January, 2001, pp. 134-139.
• "Embedded core testing using genetic algorithms," (pdf)
  Ruofan Xu and Michael S. Hsiao,
  Proceedings of the IEEE Asian Test Symposium, December, 2000, pp. 254-259.
• "Advanced behavioral-level design-for-testability techniques,"
  Sandhya Seshadri,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, November 2000.
• "Formal Operator Testability Methods for Behavioral-Level DFT Using Value Ranges," (pdf)
  Sandhya Seshadri and Michael S. Hsiao,
  Proceedings of the 5th IEEE International Workshop on High Level Design Validation and Test, November, 2000.
• "Testability evaluation and test generation for system-on-a-chip,"
  Ruofan Xu,
  M.S. Thesis , Department of Electrical and Computer Engineering, Rutgers University, July 2000.
• "Evaluation for controllability and observability of embedded cores in SOC,"
  Ruofan Xu and Michael S. Hsiao,
  in 7th IEEE International Test Synthesis Workshop, March, 2000.
• "Formal value-range and variable testability techniques for high-level design-for-testability," (pdf)
  Sandhya Seshadri and Michael S. Hsiao
  in the Journal of Electronic Testing Theory and Applications, vol. 16, no. 1/2, pp. 131-145, February, 2000.
• "An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques," (pdf)
  Sandhya Seshadri and Michael S. Hsiao,
  Proceedings of The IEEE International Test Conference, Sept., 1999, pp. 858-867.
• "State analysis based partial scan techniques to explicitly aid sequential test generation,"
  Sameer Sharma,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, July 1999.
• "Partial scan using multi-hop state reachability analysis," (pdf)
  Sameer Sharma and Michael S. Hsiao,
  Proceedings of The IEEE VLSI Test Symposium, April, 1999, pp. 121-126.
• "Partial scan selection based on dynamic reachability and observability information," (pdf)
  Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, and Janak H. Patel,
  Proceedings of the IEEE International Conference on VLSI Design, Jan., 1998, pp. 174-180.
• "Partial scan beyond cycle cutting," (pdf)
  Gurjeet S. Saund, Michael S. Hsiao, and Janak H. Patel,
  in Proceedings of the IEEE Fault Tolerant Computing Symposium, Jun., 1997, pp. 320-328.
• "Partial scan beyond cycle cutting,"
  Gurjeet S. Saund, Michael S. Hsiao, and Janak H. Patel, 4th International Test Synthesis Workshop, May, 1997

Test set compaction

This research is supported in part by:
NSF, NJCST, Fujitsu.

• "State and fault information for compaction-based test generation," (pdf)
  Ashish Giani, Shuo Sheng, Michael S. Hsiao, and Vishwani Agrawal,
  in the Journal of Electronic Testing: Theory and Applications, vol. 18, no. 1, pp. 63-72, February, 2002.
• "Compaction-based test generation using state and fault information," (pdf)
  Ashish Giani, Shuo Sheng, Michael S. Hsiao, and Vishwani Agrawal,
  Proceedings of the IEEE Asian Test Symposium, December, 2000, pp. 159-164.
• "Test set compaction using relaxed subsequence removal," (pdf)
  Michael S. Hsiao and Srimat T. Chakradhar,
  in the Journal of Electronic Testing: Theory and Applications, vol. 16, no. 4, pp. 319-327, August, 2000.
• "Test set and fault partitioning techniques for static test sequence compaction of sequential circuits," (pdf)
  Michael S. Hsiao and Srimat T. Chakradhar,
  in the Journal of Electronic Testing Theory and Applications, vol. 16, no. 4, pp. 329-338, August, 2000.
• "Study of compaction-based ATPG for sequential circuits,"
  Ashish Giani,
  M.S. Thesis , Department of Electrical and Computer Engineering, Rutgers University, June 2000.
• "On using static compaction for weighted random test patterns,"
  Ankur Jain, Vishwani Agrawal, and Michael S. Hsiao,
  6th IEEE International Test Synthesis Workship, March, 1999.
• "Fast static compaction algorithms for sequential circuit test vectors," (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in IEEE Trans. on Computers, vol. 48, no. 3, pp. 311-322, March 1999.
• "Partitioning and reordering techniques for static test sequence compaction of sequential circuits," (pdf)
  Michael S. Hsiao and Srimat T. Chakradhar,
  Proceedings of the IEEE Asian Test Symposium, Dec., 1998, pp. 452-457. (Also in NEC USA Tech. Report #97-C074-4-5506-5, November 1997.)
• "State relaxation based subsequence removal for fast static compaction in sequential circuits," (pdf)
  Michael S. Hsiao and Srimat T. Chakradhar,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, Feb., 1998, pp. 577-582. (Also in NEC USA, Tech. Report #97-C053-4-5506-2, September 1997.)
• "Fast algorithms for static compaction of sequential circuit test vectors," (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in Proceedings of the IEEE VLSI Test Symposium, Apr., 1997, pp. 188-195.

Design verification and diagnosis

This research is supported in part by:
NSF, NJCST, Intel, Fujitsu, SRC.

• "DELV: Datasheet/English to Logic Verification,"
  Edward Carlisle, Steven Frederikson, Jonathan Graf, Scott Harper, John Aromando, and Michael S. Hsiao,
  in Government Microcircuit Applications & Critical Technology Conf., Mar. 2021.
• "Formal Validation For Natural Language Programming Using Hierarchical Finite State Automata,"
  Yue Zhan and Michael S. Hsiao,
  in 13th Conference on Agents and Artificial Intelligence, Feb., 2021.
• "Mutant space optimization for RTL test generation,"
  Kunal Bansal and Michael S. Hsiao,
  in Proceedings of the International Conference on Computer Design, Oct. 2018.
• "Guiding RTL test generation using relevant potential invariants,"
  Tania Khanna and Michael S. Hsiao,
  in Proceedings of the International Conference on Computer Design, Oct. 2018.
• "Improving Bio-Inspired Frameworks,"
  Aravind Krishnan Varadarajan,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, August 2018.
• "Guiding RTL Test Generation Using Relevant Potential Invariants,"
  Tania Khanna,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, June 2018.
• "Increasing Branch Coverage with Dual Metric RTL Test Generation,"
  Kunal Bansal,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, June 2018.
• "An online framework for diagnosis of multiple defects in scan chains,"
  Sarmad Tanwir and Michael S. Hsiao,
  in Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2018.
• "Online Techniques for Enhancing Diagnosis of Digital Circuits,"
  Sarmad Tanwir,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, February 2018.
• "Fast search-based RTL test generation using control-flow path guidance,"
  Sonal Pinto and Michael S. Hsiao,
  in Proceedings of the International Conference on Computer Design, Nov. 2017.
• "RTL Functional Test Generation Using Factored Concolic Execution,"
  Sonal Pinto and Michael S. Hsiao,
  in Proceedings of the International Test Conference, Oct. 2017.
• "Reachability analysis in RTL circuits using k-induction bounded model checking,"
  Tonmoy Roy and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, October, 2017.
• "A test pattern quality metric for diagnosis of multiple stuck-at and transition faults,"
  Sarmad Tanwir, Michael S. Hsiao, and Loganathan Lingappan,
  in Proceedings of the ACM Great Lakes Symposium on VLSI, May 2017.
• "A framework for fast test generation at the RTL,"
  Kelson Gent, Akash Agrawal, and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Test Symposium, April 2017.
• "Hardware-in-the-loop model-less diagnostic test generation,"
  Sarmad Tanwir, Michael S. Hsiao, and Loganathan Lingappan,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, October, 2016.
• "Fast multi-level test generation at the RTL,"
  Kelson Gent and Michael S. Hsiao,
  in Proceedings of the IEEE Annual Symposium on VLSI, July 2016.
• "A control path aware metric for grading functional test vectors,"
  Kelson Gent and Michael S. Hsiao,
  in Proceedings of the IEEE Latin American Test Symposium, April 2016.
• "SI-SMART: functional test generation for RTL circuits using loop abstraction and learning recurrence relationships,"
  Prateek Puri and Michael S. Hsiao,
  in Proceedings of the IEEE International Conference on Computer Design, October 2015.
• "Information-theoretic and statistical methods of failure log selection for improved diagnosis,"
  Sarmad Tanwir, Sarvesh Prabhu, Michael S. Hsiao, and Loganathan Lingappan,
  in Proceedings of the IEEE International Test Conference, October 2015.
• "Design Validation of RTL Circuits using Binary Particle Swarm Optimization and Symbolic Execution,"
  Prateek Puri,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, August 2015.
• "Fast stimuli generation for design validation of RTL circuits using binary particle swarm optimization,"
  Prateek Puri and Michael S. Hsiao,
  in Proceedings of the IEEE International Sympoisum on VLSI, July 2015.
• "Branch guided functional test generation at the RTL,"
  Vineeth Acharya, Sharad Bagri, and Michael S. Hsiao,
  in Proceedings of the IEEE European Test Symposium, May 2015.
• "Branch Guided Metrics for Functional and Gate-level Testing,"
  Vineeth Acharya,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, March 2015.
• "Improving Branch Coverage in RTL Circuits with Signal Domain Analysis and Restrictive Symbolic Execution,"
  Sharad Bagri,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, March 2015.
• "Strategies for Quality and Performance Improvement of Hardware Verification and Synthesis Algorithms,"
  Mahmoud Elbayoumi,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2014.
• "Techniques for Enhancing Test and Diagnosis of Digital Circuits,"
  Sarvesh Prabhu,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2014.
• "A diagnosis-friendly LBIST architecture with property checking",
  Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, October 2014.
• "A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms,"
  Mahmoud El-bayoumi, Michael S. Hsiao, and Mustafa ElNainay,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March, 2013.
• "Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies,"
  Huy Nguyen and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, November 2012.
• "Design validation of RTL circuits using evolutionary swarm intelligence,"
  Min Li, Kelson Gent, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, November, 2012.
• "Ensuring trust of third-party hardware design with constrained sequential equivalence checking,"
  Gyanendra Shrestha and Michael S. Hsiao,
  in Proceedings of IEEE International Conf. on Technologies for Homeland Security, Nov. 2012.
• "Acceleration of hardware testing and validation algorithms using graphics processing units,"
  Min Li,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2012.
• "Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking,"
  Gyanendra Shrestha,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2012.
• "A SMT-based diagnostic test generation method for combinational circuits,"
  Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan and Vijay Gangaram,
  in Proceedings of the IEEE VLSI Test Symposium, April 2012.
• "A scan pattern debugger for partial scan industrial designs,"
  Kameshwar Chandrasekar, Supratik K. Misra, Sanjay Sengupta, and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2012.
• "An Efficient 2-Phase Strategy to Achieve High Branch Coverage,"
  Sarvesh Prabhu,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, February 2012.
• "Efficient Graph Techniques for Partial Scan Pattern Debug and Bounded Model Checkers,"
  Supratik Misra,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, February 2012.
• "Sufficiency-based filtering of invariants for sequential equivalence checking,"
  Wei Hu, Huy Nguyen, and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, November 2011.
• "Utilizing GPGPUs for design validation with a modified ant colony optimization,"
  Min Li, Kelson Gent and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, November 2011.
• "An efficient 2-phase strategy to achieve high branch coverage,"
  Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram and Jim Grundy, in Proceedings of the IEEE Asian Test Symposium, November 2011.
• "High-performance diagnostic fault simulation on GPUs,"
  Min Li and Michael S. Hsiao,
  in Proceedings of the IEEE European Test Symposium, May 2011.
• "A novel learning framework for state space exploration based on search state extensibility relation," (pdf)
  Maheshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Design Conference, January 2011, pp. 64-69.
• "Trace buffer-based silicon debug with lossless compression," (pdf)
  Sandesh Prabhakar, Rajamani Sethuram, and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Design Conference, January 2011, pp. 358-363.
• "Mining complex boolean expressions for sequential equivalence checking," (pdf)
  Neha Goel, Michael S. Hsiao, Naren Ramakrishnan, and Mohammed J. Zaki,
  in Proceedings of the IEEE Asian Test Symposium, December 2010, pp. 442-447.
• "Tackling the path explosion problem in symbolic execution-driven test generation," (pdf)
  Saparya Krishnamoorthy, Michael S. Hsiao, and Loganathan Lingappan,
  in Proceedings of the IEEE Asian Test Symposium, December 2010, pp. 59-64.
• "DFT + DFD: an integrated method for design for testability and diagnosability," (pdf)
  Nikhil Rahagude, Maheshwar Chandrasekar, and Michael S. Hsiao,
  in Proceedings of the IEEE Asian Test Symposium, December 2010, pp. 218-223.
• "Search State Extensibility-based Learning for Model Checking and Test Generation,"
  Maheshwar Chandrasekar,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2010.
• "Mining Multi-Node Constraints and Boolean Expressions for Sequential Equivalence Checking,"
  Neha Goel,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, August 2010.
• "Strategies for Scalable Symbolic Execution-based Test Generation,"
  Saparya Krishnamoorthy,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, July 2010.
• "Identification of illegal states in a discrete transition model of apoptosis signaling,"
  Anupam Srivastava, Huy Lam, Michael S. Hsiao, David Samuels, Carla Finkielstein,
  in Int'l Workshop on Bio-Design Automation (IWBDA), June 2010.
• "Trusted RTL: Trojan detection methodology in pre-silicon designs," (pdf)
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the IEEE Hardware-Oriented Security and Trust Symposium, June 2010, pp. 56-59.
• "Search state compatibility based incremental learning framework and output deviation based X-filling for diagnostic test generation,"
  Maheshwar Chandrasekar, Nikhil P. Rahagude and Michael S. Hsiao,
  in Journal of Electronic Testing: Theory and Applications, vol. 26, no. 2, pp. 165-176, April 2010.
• "Reversible logic synthesis through ant colony optimization," (pdf)
  Min Li, Yexin Zheng, Michael S. Hsiao, and Chao Huang,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, April 2010, pp. 307-310.
• "Multiplexed trace signal selection using non-trivial implication-based correlation," (pdf)
  Sandesh Prabhakar and Michael S. Hsiao,
  in Proceedings of the IEEE Symposium on Quality Electronic Design, March, 2010, pp. 697-704.
• "Exploring Hybrid Dynamic and Static Techniques for Software Verification,"
  Xueqi Cheng,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, February 2010.
• "Algorithms and Low-cost Architectures for Trace Buffer-Based Silicon Debug,"
  Sandesh Prabhakar,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2009.
• "Using non-trivial logic implications for trace buffer-based silicon debug," (pdf)
  Sandesh Prabhakar and Michael S. Hsiao,
  in Proceedings of the IEEE Asian Test Symposium, November 2009, pp. 131-136.
• "Diagnostic test generation for silicon diagnosis with an incremental learning framework based on search state compatibility,"
  Maheshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, pp. 68-75, November 2009.
• "Search state compatibility and learning for state space exploration,"
  Maheshwar Chandrasekar and Michael S. Hsiao,
  in TECHCON, September 2009.
• "VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs,"
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the Hardware-Oriented Security and Trust Workshop, July 2009.
• "Exploring Abstraction Techniques for Scalable Bit-Precise Verification of Embedded Software,"
  Nannan He,
  Ph.D. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, May 2009.
• "Design and Verification of Privacy and User Re-authentication Systems,"
  Harini Jagadeesan,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, May 2009.
• "Cognitive radio and networking research at Virginia Tech,"
  Allen B. MacKenzie, Jeffrey H. Reed, Peter Athanas, Charles W. Bostian, R. Michael Buehrer, Luiz A. DaSilva, Steven W. Ellingson, Y. Thomas Hou, Michael S. Hsiao, Jung-Min Park, Cameron Patterson, Sanjay Raman, and Claudio R. C. M. da Silva,
  Proceedings of the IEEE, vol. 97, no. 4, April 2009, pp. 660-688.
• "An efficient path-oriented bit-vector encoding width computation algorithm for bit-precise verification,"
  Nannan He and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, April 2009, pp. 1602-1607.
• "Boosting SAT solver performance via a new hybrid approach," (pdf)
  Lei Fang and Michael S. Hsiao,
  Journal on Satisfiability, Boolean Modeling and Computation, vol. 5, June 2008, pp. 57-75.
• "On dynamic switching of navigation for semi-formal design validation," (pdf)
  Ankur Parikh and Michael S. Hsiao,
  Proceedings of the IEEE High Level Design Validation and Test Workshop, pp. 41-48, November 2008.
• "SAT-based state justification with adaptive mining of invariants," (pdf)
  Weixin Wu and Michael S. Hsiao,
  in International Test Conf., October 2008.
• "Ant colony optimization directed program abstraction for software bounded model checking," (pdf)
  Xueqi Cheng and Michael S. Hsiao,
  in Proceedings of the IEEE International Conf. Computer Design, pp. 46-51, October 2008.
• "Minimum search state based learning: an efficient preimage computation technique,"
  Mahesh Chandrasekar and Michael S. Hsiao,
  in TECHCON, September 2008.
• "A new testability guided abstraction to solving bit-vector formula,"
  Nannan He and Michael S. Hsiao,
  in International Workshop on Bit-Precise Reasoning, July 2008.
• "Exploring Constraint Satisfiability Techniques in Formal Verification,"
  Lei Fang,
  Ph.D. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, May 2008.
• "A new hybrid static/run-time secure memory access protection,"
  Nannan He, Xueqi Cheng, and Michael S. Hsiao,
  in Proceedings of IEEE International Conf. on Technologies for Homeland Security, May 2008.
• "A new security sensitivity measurement for software variables,"
  Xueqi Cheng, Nannan He, and Michael S. Hsiao,
  in Proceedings of IEEE International Conf. on Technologies for Homeland Security, May 2008.
• "SAT-based equivalence checking of threshold logic designs for nanotechonologies," (pdf)
  Yexin Zheng, Michael S. Hsiao, and Chao Huang,
  in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, April 2008, pp. 225-230.
• "Efficient design validation based on cultural algorithms," (pdf)
  Weixin Wu and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2008, pp. 402-407.
• "Simulation-directed invariant mining for software verification," (pdf)
  Xueqi Cheng and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2008, pp. 682-687.
• "A fast approximation algorithm for MIN-ONE SAT," (pdf)
  Lei Fang and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2008, pp. 1087-1090.
• "Mining global constraints with domain knowledge for improving bounded sequential equivalence checking," (pdf)
  Weixin Wu and Michael S. Hsiao,
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, Jan. 2008, pp. 197-201.
• "Hybrid testing and verification techniques for a cognitive radio system,"
  Xueqi Cheng, Nannan He, and Michael S. Hsiao,
  Proceedings of the International Conf. on Software Engineering and Applications, November 2007, pp. 240-245.
• "Mining-guided state justification with partitioned navigation tracks," (pdf)
  Ankur Parikh, Weixin Wu, and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, Oct. 2007.
• "Bounded model checking of embedded software in wireless cognitive radio systems" (pdf)
  Nannan He and Michael S. Hsiao,
  in Proceedings of the IEEE International Conference on Computer Design, Oct., 2007, pp. 19-24.
• "Mining-guided sequential ATPG with partitioned navigation tracks for design validation,"
  Weixin Wu and Michael S. Hsiao,
  in TECHCON, September 2007.
• "Discrete Transition System Model and Verification for Mitochondrially Mediated Apoptosis Signaling Pathways,"
  Huy Lam,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, June 2007.
• "Abstraction Guided Semi-formal Verification,"
  Ankur Parikh,
  M.S. Thesis,, Bradley Department of Electrical and Computer Engineering, Virginia Tech, June 2007.
• "Integrating validation and verification in the digital design curriculum," (pdf)
  Shrirang Yardi and Michael S. Hsiao,
  in Proceedings of the International Conference on Microelectronic Systems Education, June 2007, pp. 143-144.
• "Using scan-dump values to improve functional-diagnosis methodology," (pdf)
  Vishnu Vimjam, Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, and Kai Yang,
  in Proceedings of the IEEE VLSI Test Symposium, May, 2007, pp. 231-238.
• "A new hybrid solution to boost SAT solver performance," (pdf)
  Lei Fang and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2007, pp. 1307-1313.
• "Strategies for SAT-based formal verification,"
  Vishnu Vimjam,
  Ph.D. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, January 2007.
• "Explicit safety property strengthening in SAT-based induction," (pdf)
  Vishnu Vimjam and Michael S. Hsiao,
  in Proceedings of the IEEE International Conf. VLSI Design, January 2007, pp. 63-68.
• "A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage," (pdf)
  Liang Zhang, Indradeep Ghosh, and Michael S. Hsiao,
  in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, November 2006, pp. 2526-2538.
• "A new simulation-based property checking algorithm based on partitioned alternative search space traversal," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  in IEEE Transactions on Computers, vol. 55, no. 11, November, 2006, pp. 1325-1334.
• "Using symbolic simulation and weakening abstraction for formal verification of embedded software,"
  Nannan He and Michael S. Hsiao,
  in Proceedings of the International Conf. on Software Engineering and Applications, November 2006, pp. 334-339.
• "Simulation-based internal variable range coverage metric and test generation model,"
  Xueqi Cheng and Michael S. Hsiao,
  in Proceedings of the International Conf. on Software Engineering and Applications, November 2006, pp. 352-357.
• "State variable extraction and partitioning to reduce problem complexity for ATPG and design validation," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  in the IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, Oct. 2006, pp. 2275-2282.
• "Characteristic states & cooperative game based search for efficient sequential ATPG and design validation," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conf., paper 24.2, October 2006.
• "Implicit search-space aware cofactor expansion: a novel preimage computation technique,"
  Kameshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE International Conf. on Computer Design, October 2006.
• "A complete & practical approach to ensure the legality of a signal transmitted by a cognitive radio,"
  Patrick Cowhig,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2006.
• "Fast illegal state identification for improving SAT-based induction," (pdf)
  Vishnu Vimjam and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation Conf., July 2006, pp. 241-246.
• "Mining global constraints for improving bounded sequential equivalence checking," (pdf)
  Weixin Wu and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation Conf., July 2006, pp. 743-748.
• "Search-space aware learning technqiues for unbounded model checking and path delay testing,"
  Kameshwar Chandrasekar ,
  Ph.D Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, April 2006.
• "Increasing the deductibility in CNF instances for efficient SAT-based bounded model checking," (pdf)
  Vishnu Vimjam and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, November 2005, pp. 184-191.
• "A new simulation-based property checking algorithm based on partitioned alternative search space traversal," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, November 2005, pp. 121-126.
• "VERISEC: VERIfying Equivalence of SEquential Circuits using SAT," (pdf)
  Manan Syal and Michael S. Hsiao,
  in Proceedings of the IEEE High Level Design Validation and Test Workshop, November 2005, pp. 52-59.
• "Interleaved invariant checking with dynamic abstraction,"
  Liang Zhang, Mukul R Prasad, and Michael S. Hsiao,
  in Proceedings of the ACM Conf. on Correct Hardware Design and Verification Methods, October 2005, pp. 81-96.
• "State set management for SAT-based unbounded model checking," (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE International Conference on Computer Design, October 2005, pp. 585-590.
• "Static learning for problems in VLSI test and verification,"
  Manan Syal ,
  Ph.D Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, June 2005.
• "Dynamic abstraction using SAT-based BMC," (pdf)
  Liang Zhang, Mukul R. Prasad, Michael S. Hsiao, and Thomas Sidle,
  in the IEEE/ACM Design Automation Conference, June 2005, pp. 754-757.
• "Forward image computation with backtracing ATPG and incremental state-set construction," (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, April 2005, pp. 254-259.
• "An effective and efficient ATPG-based combinational equivalence checker," (pdf)
  Ronald P. Lajaunie and Michael S. Hsiao,
  in Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI, April 2005, pp. 248-253.
• "Error diagnosis of sequential circuits using region-based model," (pdf)
  Anand Lloyd D'Souza and Michael S. Hsiao,
  in the Journal of Electronic Testing Theory and Applications, vol. 21, no. 2, pp. 115-126, April 2005.
• "Design verification for sequential systems at various abstraction levels,"
  Liang Zhang,
  Ph.D Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, January 2005.
• "Q-PREZ: QBF evaluation using partition, resolution and elimination with ZBDDs," (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Design Conference, January 2005, pp. 189-194.
• "Using global structural relationships of signals to accelerate SAT-based combinational equivalence checking," (pdf)
  Rajat Arora and Michael S. Hsiao,
  in the Journal of Universal Computer Science, vol. 10, no. 12, pp. 1597-1628, December 2004.
• "Success-driven learning in ATPG for preimage computation," (pdf)
  Shuo Sheng and Michael S. Hsiao,
  in the IEEE Design & Test of Computers, vol. 21, no. 6, pp. 504-512, November-December 2004.
• "CNF formula simplification using implication reasoning," (pdf)
  Rajat Arora and Michael S. Hsiao,
  in Proceedings of the IEEE High-Level Design Validation and Test Workshop, November 2004, pp. 129-134.
• "Incremental deductive and inductive reasoning for SAT-based bounded model checking," (pdf)
  Liang Zhang, Mukul R. Prasad, and Michael S. Hsiao,
  in Proceedings of the IEEE International Conference on Computer Aided Design, November 2004, pp. 502-509.
• "Decision selection and learning for an 'all solutions ATPG engine', " (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, October 2004, pp. 607-616.
• "State variable extraction to reduce problem complexity for ATPG and design validation," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  in Proceedings of the IEEE International Test Conference, October 2004, pp. 820-829.
• "Verification of Large Scale Nano Systems with Unreliable Nano Devices,"
  Michael S. Hsiao, Shuo Sheng, Rajat Arora, Ankur Jain, and Vamsi Boppana,
  book chapter in Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, edited by Sandeep Shukla and R. Iris Bahar, Kluwer Academic Publishers, Boston, MA, pp. 323-351, 2004.
• "Incrementally improving SAT-based bounded model checking,"
  Liang Zhang, Mukul R. Prasad, and Michael S. Hsiao,
  in Proceedings of the IEEE International Workshop on Logic and Synthesis, June 2004.
• "Enhancing SAT-based formal verification methods using global learning,"
  Rajat Arora,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, May 2004.
• "Efficient ATPG for design validation based on partitioned state exploration histories," (pdf)
  Qingwei Wu and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Test Symposium, April 2004, pp. 389-394.
• "A novel SAT all-solutions solver for efficient preimage computation," (pdf)
  Bin Li, Michael S. Hsiao, and Shuo Sheng
  in Proceedings of the IEEE/ACM Design Automation and Test in Europe (DATE) Conference, February, 2004, pp. 272-277.
• "Enhancing SAT-based bounded model checking using sequential logic implications," (pdf)
  Rajat Arora and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Design Conference, January, 2004, pp. 784-787.
• "Automatic design validation framework for HDL description via RTL ATPG," (pdf)
  Liang Zhang, Michael S. Hsiao, and Indradeep Ghosh,
  Proceedings of the IEEE Asian Test Symposium, November 2003, pp. 148-153.
• "ATPG-based preImage computation: efficient search space pruning with ZBDD," (pdf)
  Kameshwar Chandrasekar and Michael S. Hsiao,
  Proceedings of the IEEE High-Level Design Validation and Test Workshop, November 2003, pp. 117-122.
• "Enhancing SAT-based equivalence checking with static logic implications," (pdf)
  Rajat Arora and Michael S. Hsiao,
  Proceedings of the IEEE High-Level Design Validation and Test Workshop, November 2003, pp. 63-68.
• "ATPG based preimage computation: efficient search space pruning using ZBDD,"
  Kameshwar Chandrasekar,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, July 2003.
• "Testing and verification by exploring circuit properties,"
  Shuo Sheng,
  Ph.D. Dissertation, Department of Electrical and Computer Engineering, Rutgers University, July 2003.
• "A novel ATPG for formal verification,"
  Shuo Sheng and Michael S. Hsiao,
  Proceedings of the IEEE Microprocessor Test and Verification Workshop, May 2003.
• "High-level automatic test generation for design verification,"
  Liang Zhang, Michael S. Hsiao, and Indradeep Ghosh,
  10th IEEE International Test Synthesis Workshop, March, 2003.
• "Efficient preimage computation using a novel success-driven ATPG," (pdf)
  Shuo Sheng and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2003, pp. 822-827.
• "Effective safety property checking using simulation-based ATPG," (pdf)
  Shuo Sheng, Koichiro Takayama, and Michael S. Hsiao,
  Proceedings of the IEEE Design Automation Conference, June 2002, pp. 813-818.
• "Practical use of sequential ATPG for model checking: going the extra mile does pay off,"
  Michael S. Hsiao and Jawahar Jain,
  Proceedings of the 6th IEEE International Workshop on High Level Design Validation and Test, November, 2001, pp. 39-44.
• "On efficient error diagnosis of digital circuits," (pdf)
  Nandini Sridhar and Michael S. Hsiao,
  Proceedings of the IEEE International Test Conference, October, 2001, pp. 678-687.
• "On efficient error diagnosis of digital circuits,"
  Nandini Sridhar,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, March, 2001.
• "Techniques to improve error diagnosis accuracy and resolution,"
  Nandini Sridhar and Michael S. Hsiao,
  in 8th IEEE International Test Synthesis Workshop, March, 2001.
• "Error diagnosis of sequential circuits using region-based model," (pdf)
  Anand L. D'Souza and Michael S. Hsiao,
  Proceedings of the IEEE VLSI Design Conference, January, 2001, pp. 103-108.
• "Testing, verification, and diagnosis in the presence of unknowns,"
  Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Michael S. Hsiao, Masahiro Fujita,
  TAPTechnology, July, 2000.
• "Test quality and error diagnosis using region-based model,"
  Anand Lloyd D'Souza,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, June 2000.
• "Testing, verification, and diagnosis in the presence of unknowns," (pdf)
  Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Michael S. Hsiao, Masahiro Fujita,
  Proceedings of The IEEE VLSI Test Symposium, April, 2000, pp. 263-269.
• "Fast Defect Coverage Estimation and Diagnosis of Sequential Circuits,"
  Anand L. D'Souza and Michael S. Hsiao,
  in 7th IEEE International Test Synthesis Workshop, March, 2000.
• "On arbitrary defects: modeling and applications,"
  Ankur Jain,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, June 1999.
• "On the evaluation of arbitrary defect coverage of test sets," (pdf)
  Ankur Jain, Vamsi Boppana, Michael S. Hsiao, Masahiro Fujita,
  Proceedings of the IEEE VLSI Test Symposium, 1999, pp. 426-432.

Fault and defect coverage simulation

This research is supported in part by:
NSF, NJCST, Fujitsu.

• "Fast fault coverage estimation of sequential tests using entropy measurements,"
  Sarmad Tanwir and Michael S. Hsiao,
  in Proceedings of the IEEE VLSI Test Symposium, April 2018.
• "RAG: An efficient reliability analysis of logic circuits on graphics processing units,"
  Min Li and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2012.
• "Three-dimensional parallel fault simulation with GPGPU,"
  Min Li and Michael S. Hsiao,
  in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 10, October 2011, pp. 1545-1555.
• "High-performance diagnostic fault simulation on GPUs,"
  Min Li and Michael S. Hsiao,
  in Proceedings of the IEEE European Test Symposium, May 2011.
• "FSimGP²: an efficient fault simulator with GPGPU," (pdf)
  Min Li and Michael S. Hsiao,
  in Proceedings of the IEEE Asian Test Symposium, December 2010, pp. 15-20.
• "Fault Simulation and Test Generation,"
  James C.-M. Li and Michael S. Hsiao,
  book chapter in Electronic Design Automation: Synthesis, Verification, and Test, edited by Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Cheng, Morgan Kaufmann, San Francisco, CA, pp. 851-917, 2009.
• "On quality of test sets: relating fault coverage to defect coverage," (pdf)
  Anand Lloyd D'Souza and Michael S. Hsiao,
  in 37th Annual Systems Readiness Technology Conference (AUTOTESTCON), August, 2001.
• "Test quality and error diagnosis using region-based model,"
  Anand Lloyd D'Souza,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, June 2000.
• "Fast Defect Coverage Estimation and Diagnosis of Sequential Circuits,"
  Anand L. D'Souza and Michael S. Hsiao,
  in 7th IEEE International Test Synthesis Workshop, March, 2000.
• "On non-statistical techniques for fast fault coverage estimation," (pdf)
  Michael S. Hsiao,
  in the Journal of Electronic Testing Theory and Applications, vol. 15, no. 3, pp. 239-254, December 1999.
• "On arbitrary defects: modeling and applications,"
  Ankur Jain,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, June 1999.
• "On the evaluation of arbitrary defect coverage of test sets," (pdf)
  Ankur Jain, Vamsi Boppana, Michael S. Hsiao, Masahiro Fujita,
  Proceedings of the IEEE VLSI Test Symposium, 1999, pp. 426-432.
• "A fast, accurate, and non-statistical method for fault coverage estimation," (pdf)
  Michael S. Hsiao,
  Proceedings of the IEEE International Conference on Computer Aided Design, Nov. 1998, pp. 155-161.
• "A new architectural-level fault simulation using propagation prediction of grouped fault-effects" (pdf)
  Michael S. Hsiao and Janak H. Patel,
  in Proceedings of the IEEE International Conference on Computer Design, Oct., 1995, pp. 628-635.
• "Variable-delay event-driven logic and fault simulation"
  Michael S. Hsiao,
  Master's Thesis, Department of Electrical and Computer Engineering, Tech. Report CRHC-93-14/UILU-ENG-93-2226, University of Illinois, Jun., 1993

High-level and architectural low-power design

The objective of this research is to explore and develop powerful and effective high-level and architectural techniques for energy/power-efficient design technologies. The research topics include bottom-up power macro-modeling, top-down integration, capacitance and stimuli estimation, low-power networks, and compiler support for low-power architectures.

This research is supported in part by:
NSF, NJCST, NEC.

• "Novel SAT-based invariant-directed low-power synthesis,"
  Mahmoud Elbayoumi, Michael S. Hsiao, and Mustafa Elnainay,
  in Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2015.
• "Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads," (pdf)
  Shrirang Yardi and Michael S. Hsiao,
  in Proceedings of the IEEE International Conf. Computer Design, pp. 583-590, October 2008.
• "A formal framework for modeling and analysis of system-level dynamic power management," (pdf)
  Shrirang Yardi, Karthik Channakeshava, Michael S. Hsiao, Thomas Martin, and Dong S. Ha,
  in Proceedings of the IEEE International Conference on Computer Design, October 2005, pp. 119-126.
• "Region-level approximate computation reuse for power reduction in multimedia applications," (pdf)
  Xueqi Cheng and Michael S. Hsiao,
  in Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, August 2005, pp. 119-122.
• "Quality-driven proactive computation elimination for power-aware multimedia processing," (pdf)
  Shrirang Yardi, Michael S. Hsiao, Thomas Martin, and Dong Ha,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2005, pp. 340-345.
• "Approximate computation reuse for power reduction of multimedia applications,"
  Xueqi Cheng and Michael S. Hsiao
  Technical Report 2004-07-1, PROACTIVE Lab, Virginia Tech, July, 2004.
• "Denial-of-service attacks on battery-powered mobile computers," (pdf)
  Thomas Martin, Michael S. Hsiao, Dong Ha, and Jayan Krishnaswami,
  in Proceedings of the IEEE International Conference on Pervasive Computing and Communications, March, 2004, pp. 309-318.
• "Estimation of average power consumption by power macro-modeling technique,"
  Hailan Zhu,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, November 2002.
• "Reducing power consumption by utilizing retransmission in short range wireless network," (pdf)
  Yufeng Zhao and Michael S. Hsiao,
  Proceedings of the IEEE Conference on Local Computer Networks, November 2002, pp. 527-533.
• "Genetic spot optimization for peak power estimation in large VLSI circuits," (pdf)
  Michael S. Hsiao,
  in VLSI Design, vol. 15, no. 1, pp. 407-416, August 2002.
• "A hardware architecture for dynamic performance and energy adaptation," (pdf)
  Phillip Stanley-Marbell, Michael S. Hsiao, and Ulrich Kremer,
  Proceedings of Workshop on Power-Aware Computer Systems (PACS), February 2002, pp. 23-32. (also in Technical Report DCS-TR457, September 2001.)
• "Power macromodeling for high level power estimation,"
  Mayuri Vasireddi,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, July, 2001.
• "Hardware and compiler techniques for microprocessor energy reduction,"
  Phillip Stanley-Marbell
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, July, 2001.
• "Fast, flexible, cycle-accurate energy estimation," (pdf)
  Phillip Stanley-Marbell and Michael S. Hsiao,
  Proceedings of the ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2001, pp. 141-146.
• "Compiler-directed dynamic voltage/frequency scheduling for energy reducti on in microprocessors," (pdf)
  Chung-Hsing Hsu, Ulrich Kremer, and Michael S. Hsiao,
  Proceedings of the ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2001, pp. 275-278.
• "Accurate power macro-modeling techniques for complex RTL circuits," (pdf)
  Nachiketh R. Potlapally, Anand Raghunathan, Ganesh Lakshmininarayana, Michael S. Hsiao, and Srimat T. Chakradhar,
  Proceedings of the IEEE VLSI Design Conference, January, 2001, pp. 235-241.
• "Fast, cycle-accurate energy estimation for networks of embedded systems,"
  Phillip Stanley-Marbell and Michael S. Hsiao,
  CAIP Technical Report TR-255, Department of Electrical and Computer Engineering, Rutgers University, December, 2000.
• "Compiler-directed dynamic frequency and voltage scheduling," (pdf)
  Chung-Hsing Hsu, Ulrich Kremer, and Michael S. Hsiao,
  Proceedings of Workshop on Power-Aware Computer Systems (PACS), November 2000.
• "High level power estimation techniques,"
  Nachiketh Potlapally,
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, August 2000.
• "Accurate power macro-modeling techniques for complex RTL circuits,"
  Nachiketh R. Potlapally, Anand Raghunathan, Ganesh Lakshmininarayana, Michael S. Hsiao, and Srimat T. Chakradhar,
  NEC USA Technical Report 2000-C037-4-5056-3, August, 2000.

Gate-level power dissipation in VLSI

• "Energy-efficient logic BIST based on state correlation analysis," (pdf)
  Xiaoding Chen and Michael S. Hsiao,
  Proceedings of the IEEE VLSI Test Symposium, April 2003, pp. 267-272.
• "Peak power estimation of VLSI circuits: new peak power measures," (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in the IEEE Transactions of VLSI Systems, vol. 8, no. 4, pp. 435-439, August, 2000.
• "Peak power estimation using genetic spot optimization for large VLSI circuits," (pdf)
  Michael S. Hsiao,
  Proceedings of the IEEE Design, Automation, and Test in Europe Conference, Mar., 1999, pp. 175-179.
• "A new approach to peak power estimation of VLSI circuits,"
  Michael S. Hsiao,
  CAIP Update,, vol. 11, No. 3, 1998.
• "Effects of delay model in peak power estimation of VLSI sequential circuits," (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in Proceedings of the IEEE International Conference on Computer Aided Design, Nov., 1997, pp. 45-51.
• "K2: An estimator for peak sustainable power of VLSI circuits," (pdf)
  Michael S. Hsiao, Elizabeth M. Rudnick, and Janak H. Patel,
  in Proceedings of the IEEE International Symposium on Low Power Electronics and Design, Aug., 1997, pp. 178-183.

Computer Architecture

This research is supported in part by:
NSF, NJCST.

• "Region-level approximate computation reuse for power reduction in multimedia applications," (pdf)
  Xueqi Cheng and Michael S. Hsiao,
  in Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, August 2005, pp. 119-122.
• "Quality-driven proactive computation elimination for power-aware multimedia processing," (pdf)
  Shrirang Yardi, Michael S. Hsiao, Thomas Martin, and Dong Ha,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2005, pp. 340-345.
• "Approximate computation reuse for power reduction of multimedia applications,"
  Xueqi Cheng and Michael S. Hsiao
  Technical Report 2004-07-1, PROACTIVE Lab, Virginia Tech, July, 2004.
• "A hardware architecture for dynamic performance and energy adaptation," (pdf)
  Phillip Stanley-Marbell, Michael S. Hsiao, and Ulrich Kremer,
  Proceedings of Workshop on Power-Aware Computer Systems (PACS), February 2002, pp. 23-32.
• "Hardware and compiler techniques for microprocessor energy reduction,"
  Phillip Stanley-Marbell
  M.S. Thesis, Department of Electrical and Computer Engineering, Rutgers University, July, 2001.
• "Fast, flexible, cycle-accurate energy estimation," (pdf)
  Phillip Stanley-Marbell and Michael S. Hsiao,
  Proceedings of the ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2001, pp. 141-146.
• "Compiler-directed dynamic voltage/frequency scheduling for energy reducti on in microprocessors," (pdf)
  Chung-Hsing Hsu, Ulrich Kremer, and Michael S. Hsiao,
  Proceedings of the ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2001, pp. 275-278.
• "Exploring the interaction between Java's implicitly thrown exceptions and instruction scheduling," (pdf)
  Matthew Arnold, Michael S. Hsiao, Ulrich Kremer, and Barbara Ryder,
  in the International Journal of Parallel Programming, vol. 29, no. 2, pp. 111-137, April, 2001.
• "Fast, cycle-accurate energy estimation for networks of embedded systems,"
  Phillip Stanley-Marbell and Michael S. Hsiao,
  CAIP Technical Report TR-255, Department of Electrical and Computer Engineering, Rutgers University, December, 2000.
• "Compiler-directed dynamic frequency and voltage scheduling," (pdf)
  Chung-Hsing Hsu, Ulrich Kremer, and Michael S. Hsiao,
  Proceedings of Workshop on Power-Aware Computer Systems (PACS), November 2000.
• "Instruction scheduling in the presence of Java's runtime exceptions," (pdf)
  Matthew Arnold, Michael S. Hsiao, Ulrich Kremer, and Barbara Ryder,
  Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing, August, 1999.
• "Instruction Scheduling in the Presence of Java's Runtime Exceptions,"
  Matthew Arnold, Michael S. Hsiao, Ulrich Kremer, and Barbara Ryder,
  Department of Computer Science, Rutgers University, Number DCS-TR-384, June, 1999.
• "Crossbar-switch-based microprocessor to exploit ILP,"
  Carlos Parodi, Michael S. Hsiao, and Vishwani Agrawal,
  1998 Mid-Atlantic Student Workshop on Programming Languages and Systems, April, 1998.

Security and Privacy

This research is supported in part by:
NSF.

• "Hardware IP Trust,"
  Mainak Banga and Michael S. Hsiao,
  book chapters in The Hardware Trojan War: Attacks, Myths, and Defenses, Springer, 2017.
• "On the uniqueness of fingerprints via mining of statistically rare features,"
  Indira Munagani, Michael S. Hsiao, and A. Lynn Abbott,
  in Proceedings of IEEE International Conf. on Technologies for Homeland Security, Apr. 2015.
• "Hardware trojan attacks: threat analysis and countermeasures,"
  Swarup Bhunia, Michael S. Hsiao, Mainak Banga, and Seetharam Narasimhan,
  in Proceedings of the IEEE, vol 102, no. 8, August 2014, pp. 1229-1247.
• "Mining Rare Features in Fingerprints using Core Points and Triplet-based Features,"
  Indira Munagani,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2013.
• "Anti-Counterfeit and Anti-Tamper Implementation using Hardware Obfuscation,"
  Avinash Desai,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, August 2013.
• "Protection against hardware trojan attacks: towards a comprehensive solution,"
  Miron Abramovici, Dakshi Agarwal, Swarup Bhunia, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, and Mohammad Tehranipoor,
  in IEEE Design & Test of Computers, May/June 2013, pp. 6-17.
• "Interlocking obfuscation for anti-tamper hardware,"
  Avinash Desai, Michael S. Hsiao, Chao Wang, Leyla Nazhandali, and Simin Hall,
  in Cyber Security and Information Intelligence Research Workshop, Jan. 2013.
• "Ensuring Trust Of Third-Party Hardware Design With Constrained Sequential Equivalence Checking,"
  Gyanendra Shrestha,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, September 2012.
• "Ensuring trust of third-party hardware design with constrained sequential equivalence checking,"
  Gyanendra Shrestha and Michael S. Hsiao,
  in Proceedings of IEEE International Conf. on Technologies for Homeland Security, Nov. 2012.
• "Reducing descriptor measurement error through Bayesian estimation of fingerprint minutia location and direction,"
  Nathan J. Short, A. Lynn Abbott, Michael S. Hsiao, and Edward A. Fox,
  in IET Biometrics, vol. 1, no. 1, March 2012, pp. 82-90.
• "A bayesian approach to fingerprint minutia localization and quality assessment using adaptable templates,"
  Nathan Short, A. Lynn Abbott, Michael S. Hsiao, and Edward Fox,
  in Proceedings of the International Joint Conference on Biometrics, October 2011.
• "Continuous Authentication in Computers,"
  Harini Jagadeesan and Michael S. Hsiao,
  book chapter in Continuous Authentication Using Biometrics: Data, Models, and Metrics, edited by Issa Traore and Ahmed Awad E. Ahmed, IGI Global, pp. 40-66, 2011.
• "Experiment and analysis services in a fingerprint digital library for collaborative research,"
  Sung Hee Park, Jonathan Leidig, Lin Tzy Li, Edward Fox, Nathan J. Short, Kevin E. Hoyle, A. Lynn Abott and Michael S. Hsiao,
  in Proceedings of the International Conference on Theory and Practice of Digital Libraries, September 2011.
• "Minutiae triplet-based features with extended ridge information for determining sufficiency in fingerprints,"
  Kevin Hoyle,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, July 2011.
• "ODETTE: A Non-Scan Design-for-Test Methodology for Trojan Detection in ICs,"
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the IEEE Hardware-Oriented Security and Trust Symposium, June 2011.
• "Testing and verifiation strategies for enhancing trust in third party IPs,"
  Mainak Banga,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, December 2010.
• "High performance scalable and expressive modeling environment to study mobile malware in large dynamic networks,"
  Karthik Channakeshava,
  Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, October 2010.
• "Rethinking fingerprint evidence through integration of very large digital libraries,"
  Nadia P. Kozievitch, Ricardo da S. Torres, Sung Hee Park, Edward A. Fox, Nathan Short, A. Lynn Abbott, Supratik Misra, and Michael S. Hsiao,
  in Proceedings of the Workshop on Very Large Digital Libraries, September 2010.
• "Toward a quantitative basis for sufficiency of friction ridge pattern detail,"
  Michael S. Hsiao, A. Lynn Abbott, Edward Fox, Randy Murch, Bruce Budowle, Nathan Short, Supratik Misra, Nadia Kozievitch, and Sung Hee Park,
  in Impression & Pattern Evidence Symposium, Aug 2010.
• "Trusted RTL: Trojan detection methodology in pre-silicon designs,"
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the IEEE Hardware-Oriented Security and Trust Symposium, June 2010, pp. 56-59.
• "A novel approach to design of user re-authentication systems,"
  Harini Jagadeesan and Michael S. Hsiao,
  in Proceedings of the IEEE Conference on Biometrics: Theory, Applic ations and Systems, September 2009, pp. 379-384.
• "VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs,"
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the Hardware-Oriented Security and Trust Workshop, July 2009.
• "Evaluation of online resources in assisting phishing detection,"
  Kaigui Bian, Jung-Min Park, Michael S. Hsiao, France Belanger, and Janine Hiller,
  in IEEE/IPSJ International Symp. on Applications and the Internet (SAINT 2009), Seattle, USA, July 2009, pp. 30-36.
• "Design and Verification of Privacy and User Re-authentication Systems,"
  Harini Jagadeesan,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, May 2009.
• "Children Online Privacy: Issues with Parental Awareness and Control,"
  France Belanger, Robert E. Crossler, Janine S. Hiller, Jung-Min Park, and Michael S. Hsiao,
  Annals of Emerging Research in Information Assurance, Security and Privacy Services, Edited by Rao, H. R. and Upadhyaya, S. (Eds.), vol. 4, 2009, Emerald Group Publishing, pp. 311-333.
• "A novel sustained vector technique for the detection of hardware trojans,"
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the IEEE International VLSI Design Conf., January, 2009, pp. 327-332.
• "Determinants of protection behaviors for online privacy of children,"
  Robert E. Crossler, France Bélanger, Janine S. Hiller, Jung-Min Park, Michael S. Hsiao, Karthik Channakeshava, Kaigui Bian, and Elizabeth Korbich,
  39th Annual Meeting of The Decision Sciences Institute (DSI), pp. 1641-1647, November, 2008.
• "POCKET Protection,"
  Janine S. Hiller, France Belanger, Michael S. Hsiao, and Jung-Min Park,
  American Business Law Journal, vol. 45, no. 3, pp. 417-453, Fall, 2008.
• "On providing automatic parental consent over information collection from children,"
  Karthik Channakeshava, Kaigui Bian, Michael S. Hsiao, Jung-Min Park, Robert Crossler, France Belanger, Payal Aggarwal, and Janine Hiller,
  International Conference on Security and Management (SAM), pp. 196-202, July 2008.
• "Parents and the internet: privacy awareness, practices, and control,"
  Robert E. Crossler, France Bélanger, Janine S. Hiller, Payal Aggarwal, Karthik Channakeshava, Kaigui Bian, Jung-Min Park, and Michael S. Hsiao,
  in Proceedings of the America's Conference on Information Systems (AMCIS), Keystone, Colorado, August 2007.
• "A region based approach for the identification of hardware trojans," (pdf)
  Mainak Banga and Michael S. Hsiao,
  in Proceedings of the Hardware-Oriented Security and Trust Workshop, pp. 40-47, June 2008.
• "A new hybrid static/run-time secure memory access protection,"
  Nannan He, Xueqi Cheng, and Michael S. Hsiao,
  in Proceedings of IEEE International Conf. on Technologies for Homeland Security, May 2008.
• "A new security sensitivity measurement for software variables,"
  Xueqi Cheng, Nannan He, and Michael S. Hsiao,
  in Proceedings of IEEE International Conf. on Technologies for Homeland Security, May 2008.
• "Towards an intrusion detection system for battery exhaustion attacks on mobile computing devices," (pdf)
  Daniel Nash, Thomas Martin, Dong Ha, and Michael S. Hsiao,
  in Proceedings of the International Workshop on Pervasive Computing and Communication Security, March 2005, pp. 141-145.
• "Denial-of-service attacks on battery-powered mobile computers," (pdf)
  Thomas Martin, Michael S. Hsiao, Dong Ha, and Jayan Krishnaswami,
  in Proceedings of the IEEE International Conference on Pervasive Computing and Communications, March, 2004, pp. 309-318.

Parallelization

• "RTL test generation on multi-core and many-core architectures,"
  Aravind Krishnan Varadarajan and Michael S. Hsiao,
  in Proceedings of the International Conference on VLSI Design, Jan. 2019.
• "An Expanded Speedup Model for the Early Phases of High Performance Computing Cluster (HPCC) Design,"
  Matthew Gabriel,
  M.S. Thesis, Bradley Department of Electrical and Computer Engineering, Virginia Tech, May 2013.
• "A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms,"
  Mahmoud El-bayoumi, Michael S. Hsiao, and Mustafa ElNainay,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March, 2013.
• "Parallel genetic algorithms for simulation based sequential circuit test generation," (pdf)
  Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Prithviraj Banerjee, and Janak H. Patel,
  in Proceedings of the 10th IEEE International Conference on VLSI Design, Jan., 1997, pp. 475-481.

Reliability and Fault-Tolerance

• "RAG: An efficient reliability analysis of logic circuits on graphics processing units,"
  Min Li and Michael S. Hsiao,
  in Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2012.
• "Reliability driven synthesis of sequential circuits,"
  Frank F. Hsu, Michael S. Hsiao, and Prithviraj Banerjee,
  Coordinated Science Laboratory, University of Illinois, Urbana, IL, Technical Report CRHC-96-2220/UILU-ENG-96-12, Sep., 1996.

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