PROACTIVE: Computer-aided Testing, Verification, and Power Management Research


The publications are listed under the following Research Areas:

Architectural-level and gate-level test generation

The test generation problem has been proven to be NP-complete. The time frame expansion in sequential circuits introduces another dimension of complexity. In spite of the complexity, significant advances have been achieved in automatic test pattern generation (ATPG) for sequential circuits in recent years. The objective of this research addresses the difficulties encountered during test generation, as well as finding solutions to overcome them.

This research is supported in part by:
NSF, SRC, NJCST, Intel, Fujitsu.

Design for testability (DFT)

A testable design relieves the high cost of test generation. However, design-for-testability frequently results in area and performance overheads. This research focuses on minimizing these overheads by exploiting information from the ATPG, circuit description, or high-level abstraction to limit the amount of extra DFT hardware on chip.

This research is supported in part by:
NSF, NJCST, Intel, Fujitsu.

Test set compaction

Test sequence compaction produces test sequences of reduced lengths, which can greatly reduce the test application time. Test application time is important because it directly impacts the cost of testing. Static test sequence compaction is done in a post-processing step to test generation and is independent of the test generation algorithm and process. Different techniques for fast static test sequence compaction are explored.

This research is supported in part by:
NSF, NJCST, Fujitsu.

Design verification and diagnosis

The increasing cost of identifying as well as correcting design errors has created the need for powerful and effective verification and diagnosis technology. The objective of this research is to develop new and innovative algorithms for VLSI and System-on-a-Chip (SOC) circuits to tackle computer-aided research problems of verification and diagnosis.

This research is supported in part by:
NSF, NJCST, Intel, Fujitsu, SRC.

Fault and defect coverage simulation

Fault simulators evaluate the effectiveness of a given test sequence and are able to speed up the test generation process by dropping faults that would be detected by the derived test vectors. Techniques to improve fault simulation and defect coverage evaluation (reductions in both memory usage and CPU time) are objectives of this research.

This research is supported in part by:
NSF, NJCST, Fujitsu.

High-level and architectural low-power design

Due to increasing complexity of the circuits and pressure to reduce the time to market, the design is done in a hierarchial fashion. In order for a design to satisfy tight power budgets, a "power conscious" design methodology needs to be adopted for all levels in the hierarchy. In adopting the power-conscious design scheme, we need tools which can estimate the power consumed by a design at all the levels of the design hierarchy, especially at the high level, for the following reason: More significant power optimization oppurtunities can be explored at the higher levels of the design hierarchy than at the lower levels. In addition, making changes to the designs at the lower levels would be costly, due to the time and effort spent in deriving the lower level structures.

The objective of this research is to explore and develop powerful and effective high-level and architectural techniques for energy/power-efficient design technologies. The research topics include bottom-up power macro-modeling, top-down integration, capacitance and stimuli estimation, low-power networks, and compiler support for low-power architectures.

This research is supported in part by:
NSF, NJCST, NEC.

Gate-level power dissipation in VLSI

The continuing decrease in feature size and increase in chip density in recent years give rise to concerns about excessive power dissipation in VLSI chips. Circuits become less reliable as large instantaneous power dissipation can cause overheating (local hot spots), and the failure rate for components roughly doubles for every 10 degrees (Celcius) increase in operating temperature. Furthermore, the growing market of portable computing products such as cellular phones and portable computers, long operational lifetime is required, which demands low power consumptions on the components. The power dissipated in CMOS logic circuits is a complex function of the gate delays, clock frequency, process parameters, circuit topology and structure, and the input vectors applied. Once the processing and structural parameters have been fixed, the measure of power dissipation is dominated by the switching activity (toggle counts) of the circuit. Because of the enormous size of the search space for finding the peak power bound, heuristics are needed to guide the search, especially in large circuits.

Computer Architecture

This research is supported in part by:
NSF, NJCST.

Security and Privacy

This research is supported in part by:
NSF.

Parallelization

Reliability and Fault-Tolerance


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