Welcome to the
ECE 5545 VLSI Circuit Design II
Homepage
Fall 2010

Professor

Dr. Joseph G. Tront
359 Durham Hall
jgtront@vt.edu
(540) 231-5067

Announcement

  • Check email and Scholar site often)
  • Send E-Mail to Class Discussion Group: ECE5545_98611@listserv.vt.edu

    • Table of Contents

  • Syllabus
  • Schedule
  • Project
  • Silicon Run video
  • SPICE Models AMI 1.5um  AMI 05.um
  • MOSIS Design Rules
  • Class Notes can be obtained using Classroom Presenter during lectures

    • Homework

  • See Scholar

    • The Use of Cadence Tools

  • VT CADENCE users guide
  • Cadence university alliance program page
  • The Setup of Cadence
  • A Tutorial to Cadence Tools: Virtuoso and Spice
  • A tutorial to Virtuoso from Penn state university
  • Instructions for plotting
  • Additional Instructions for plotting

    • Web Sites

  • The "Built-In Self-Test for Systems-on-Chip" tutorial provides online

    • access to the The 18th IEEE VLSI Test Symposium 2000 workshop
  • The Semiconductor Applet Service - A set of tutorial Java-based presentations
  • Spice Overview - Tutorial overview of SPICE
  • HPSICE Manual - Online manual for a version of SPICE
  • References - Journal Articles of interest to the class

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    Last Updated on August 2010