Class |
Date |
Topic |
Reading |
Homework |
1 |
T Aug. 24 |
Introduction; CMOS Logic Gate Design |
6.1,6.2 |
|
2 |
H Aug. 26 |
No Class |
6.3 |
|
3 |
T Aug. 31 |
Static CMOS; Ratioed Logic |
||
4 |
H Sep. 2 |
Complex Logic Gates; |
||
5 |
T Sep. 7 |
Dynamic Circuits, Pass Transistor Logic |
6.3.4-6.6 |
|
6 |
H Sep. 9 |
Circuit Pitfalls |
6.7, .6.8 |
|
7 |
T Sep. 14 |
Circuit Pifalls |
||
8 |
H Sep. 16 |
BiCMOS; Pseudo NMOS |
||
9 |
T Sep. 21 |
Dynamic CMOS; Clocked CMOS |
||
10 |
H Sep. 23 |
Pass Transistor Logic |
||
11 |
T Sep. 28 |
Domino Logic |
||
12 |
H Sep. 30 |
Cascade Voltage Switch Logic |
||
13 |
T Oct. 5 |
SFPL Logic |
||
14 |
H Oct. 7 |
Clocking Strategies - systems, latches, registers |
||
15 |
T Oct. 12 |
Timing; setup & Hold |
||
16 |
H Oct. 14 |
Timing |
||
17 |
T Oct. 19 |
Midterm Exam |
||
18 |
H Oct. 21 |
Clocking techniques |
||
19 |
T Oct. 26 |
Clocking Techniques |
||
20 |
H Oct. 28 |
Structured design strategies |
||
21 |
T Nov. 2 |
Programmable Structures |
||
22 |
H Nov. 4 |
Programmable Structures |
||
23 |
T Nov. 9 |
Standard Cell Structures |
||
24 |
H Nov. 11 |
Design Tools & Verification |
||
25 |
T Nov. 16 |
Testing Strategies |
||
26 |
H Nov. 18 |
Testing Strategies |
||
Nov. 20-28 |
Thanksgiving Break |
|||
27 |
T Nov. 30 |
BIST |
||
28 |
H Dec. 2 |
Manufacturing test |
||
29 |
T Dec 7 |
Review |
||
-- |
Dec |
Final Exam PM |