The Setup and Running of Cadence Tools

To setup the Cadence Tools

1. Make your own working directory, and enter the working directory.
2. Copy the following file cds.lib into your working directory.


3. Do the following command:
   

   	/bin/cp -r /home/ee5545jg/MOSIS ~/.  
       

4. DO NOT use the UNIX setup procedure given by the tutorial.

To run the Cadence Tools

1. You should start the following command each time you use Cadence or Spice
   
   source /home/ee5545jg/start_cadence
   
2. Follow the tutorial to run Virtuoso and Spice using the links on the main page.
3. Command hints #1: to run Virtuoso, type
   
   a). In your working directoy, type
   
           icfb&
   
   b). In icfb window,
   
           i). FILE->OPEN -- open an exisiting transistor layout.
   
                   Library Name: MOSIS
   
                   Cell Name: Inv
   
                   View Name: layout
   
           ii). FILE->NEW->cell view -- create a new transistore
   
                   Library Name: MOSIS
   
                   Cell Name: my_inv
   
                   View Name: layout
   
                   Tool: Virtuoso
   
   c). In LSW window,
   
           Edit -> Display Resource Editor -> File -> Load -> "~/MOSIS/MOSIS/display.drf"
   
4. Command hints #2: to run Spice, use the commands
   
   spectre [].spice
   for simulation, and
   
   awd -dataDir [].raw
   for drawing and plotting. Of which [] is the circuit name.
5. To view menus, use
   
   openbook& -> IC Tools -> Schematic Entry -> Composer Tutorial
   

Suggested Steps for the Project

For those who use Cadence Schematic tools

1. create schematic of your design
2. verify your result using Verilog simulator at the schematic level, you definitely have to show that your design works
3. create layout level of your design
4. extract your design to 'extracted' level (yes, you can do that, i just successfully did it myself), correct any mistakes that you may have - look at the tuturial for detail; this step is important, because it shows that your layout is the same as your schematic
5. if you have a VISC account, HSPICE is available to you, and you can extract your netlist directly from the SCHEMATIC (not layout) level of your design. otherwise, use spectre to simulate your circuit. type in your circuit. do the simulation. for either case, you may run into trouble to do spice simulation. focus on the first 4 steps, and do this step if you have time.

For those who use Synopsis tools

1. create a VHDL model
2. simulate your design
3. create layout level of your design based on the VHDL model
4. you have to find a way to somehow verify that the VHDL model is the same as your layout (i have not yet figure out how to do this myself)
5. same as 5 above

Import CIF File to Cadence

1. Copy those files cif.tf and cifmap into your project directory
2. In the "Import CIF" dialog box, at the entry which is asking "ASCII tech file", specify "./cif.tf" as your tech file.
3. In the "User-defined ..." dialog box, at the entry "Layer mapping", specify "./cifmap" as your conversion file.
4. Follow the instructions given at the Penn State Web site, and do the conversion, then input the cell view of your design to Virtuoso, it should work.