1
STARC DSG VHDL Rules

Introduction

This chapter provides reference information for the STARC Design Style Guide (DSG) coding guidelines for VHDL. The rules and guidelines in this chapter are based on the Design Style Guide Ver1.0, published by STARC. There is one policy for VHDL-based designs, documented in this chapter, and a companion policy for Verilog-based designs, documented in the STARC Design Style Guide coding guidelines for Verilog.

These policies define a design style that you can follow for HDL designs based on an intellectual property (IP) reuse methodology. There are more than 200 rules in the combined policies that you can use to ensure that your design follows the STARC recommended methodology in the following areas:

You can customize the rules in this policy to meet our own design team's requirements using the Leda Rule Configuration Wizard.

The complete documentation of each STARC rule is available via the link present at the top of each ruleset.

For more information on the STARC design style coding guidelines, see the STARC Web site at http://www.starc.or.jp/.

Each rule in this policy has a label. In general, the labels contain the following fields:

VHD | VER_S_SS_P_id

where:

VHD or VER is a prefix that indicates whether the rule applies to VHDL or Verilog.

S, SS, and P refer to the section, subsection, and paragraph, respectively, in the STARC documentation.

id is a unique integer that indicates where the rule is placed in the paragraph.

For example, rule VER_1_3_2_1 is described in the STARC documentation for Verilog Design Style Guide, section 1 (basic design constraint), subsection 1.3 (initial reset), paragraph 1.3.2 (reset line hazard).

For VHDL, the corresponding rule label is VHD_1_3_2_1.

The rules in this policy are organized into the following rulesets:

Duplicated Rules in STARC DSG for VHDL

The duplicated rules of STARC DSG for VHDL are listed in a table containing information about respective rules.

Table 2: Duplicated Rule List for VHDL 
General Description
Rule Label
Reg name should end with _reg and _REG, and should include the driving clock name.
VHD_1_1_5_1A
VHD_1_1_5_1B
VHD_1_1_5_3
Reg name should end with _reg and _REG, and should include the driving clock name.
VHD_1_1_5_1A
VHD_1_1_5_1B
VHD_1_1_5_4
Architecture names should be RTL, BEH, SIM(TB). VHD_1_1_6_1
VHD_1_1_6_2
Architecture names should be RTL, BEH, SIM(TB).
VHD_1_1_6_1
VHD_1_1_6_3
Asynchronous feedback loop detected.
VHD_1_2_1_2
VHD_1_2_1_3
Asynchronous feedback loop detected.
VHD_1_5_1_1
VHD_1_5_1_2
Do not use buffer or linkage. VHD_2_1_3_1
VHD_2_1_3_2
Do not use shift functions such as sll. VHD_2_1_4_2
VHD_2_1_4_3
Do not use operators in index of array. VHD_2_1_6_3
VHD_2_1_6_5
Use only the following attributes: range, length, left, right, high, low, reverse_range, and event. VHD_2_1_9_3
VHD_2_1_9_4
Use only the following attributes: range, length, left, right, high, low, reverse_range, and event. VHD_2_1_9_4
VHD_2_1_9_5
Do not use procedures. VHD_2_1_8_8
VHD_2_1_10_5
Use signal assignment statement in the flip-flop inference. Do not use variable assignment. VHD_2_3_1_1
VHD_2_3_2_1
Use signal assignment statement in the flip-flop inference. Do not use variable assignment. VHD_2_3_1_1
VHD_2_3_2_3
Do not initialize flip-flops in signal declaration, port declaration, and variable declaration. VHD_2_1_3_4
VHD_2_3_4_1
VHD_2_3_4_2
Asynchronous feedback loop detected. VHD_1_2_1_3
VHD_2_4_1_4
Number of nested elements in if statement should be 5 or less. VHD_2_7_3_1
VHD_2_7_3_3
Number of states in FSM should not exceed 40. VHD_2_11_1_4
VHD_2_11_1_5
Define FSM state value by using parameter. VHD_2_11_1_3
VHD_2_11_4_2
Define FSM state value by using parameter. VHD_2_11_1_3
VHD_2_11_5_1
Hard-coded value for bus size is not recommended. VHD_1_1_4_7
VHD_3_1_5_1
File names should be as follows: <entity>.vhd VHD_1_1_1_1
VHD_3_5_2_2
use name+'_pac.vhd' for package files. VHD_1_1_4_1
VHD_3_5_2_2
Define one signal per line and always add comments in I/O, register declarations and wire declarations. VHD_3_1_3_4A
VHD_3_1_3_4B
VHD_3_5_6_3

S_1_1_NAMING_CONVENTIONS Ruleset

The following rules are from the S_1_1_NAMING_CONVENTIONS ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_1_1_1_1

Message: File names should be as follows: <entity>.vhd

Description Name the files in <entity>.vhd format.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_1_2

Message: Only alphanumeric characters and the underscore '_' should be used

Description Use only alphanumeric characters and underscore '_' for naming. For example: test, clk_12mhz.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_1_3A

Message: Do not use Verilog or VHDL keywords

Description Avoid using Verilog or VHDL keywords.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_1_3B

Message: Do not use SDF, EDIF, or Window keywords

Description Avoid using SDF, EDIF or Windows keywords.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_1_4

Message: Do not use following expressions in names <VER_1_1_1_4_SIGNAL_NAME>

Description Do not use names like VDD, VSS, VCC, or GND.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_1_6

Message: Entity names and component names should be the same

Description Entity names and component names must be the same.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Error

VHD_1_1_1_7

Message: Active low signals should have suffix _X, _N

Description Active low signals should have suffix _X, _N for identification of their polarity.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_1_8

Message: Instance name should be U<instantiated entity>, If multiple instances occur, it should be U<instantiated entity>_<number>

Description Instance name should be U<instantiated_entity>. If multiple instance exist, it must be as U<instantiated_entity>_<number>.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_1_9A

Message: Top entity names should not exceed 16 characters

Description Top-level entity name should consists of 16 or fewer characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Error

VHD_1_1_1_9B

Message: Top entity name should not mix upper case and lower case

Description Top-level entity name should not mix upper- and lower-case characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Error

VHD_1_1_1_9C

Message: Top level port's name should not exceed 16 characters

Description Top-level port name should consists of 16 or fewer characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Error

VHD_1_1_1_9D

Message: Top level port's name should not mix upper-case and lower-case characters

Description Top-level port name should not mix upper- and lower-case characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Error

VHD_1_1_1_10

Message: Do not use module names or instance names that are the same as library cell names.

Description Module or instance names and library cell names should not be the same.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_2_1A

Message: Entity name should be at least 2 characters

Description Entity name should be at least 2 characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_2_1B

Message: Entity name should not exceed 32 characters

Description Entity name should not exceed 32 characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_2_1C

Message: Instance name should be at least 2 characters

Description Instance name should be at least 2 characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_2_1D

Message: Instance name should not exceed 32 characters

Description Instance name should not exceed 32 characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_2_5

Message: I/O port names should be upper case

Description I/O port names should be in upper-case.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Note

VHD_1_1_2_6

Message: In cell instantiation, pin name and net name should be the same

Description In cell instantiation, pin name and net name should be the same.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_3_1

Message: Internal net names should contain at least 1 lower case character

Description Internal net names should contain at least 1 lower-case character.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Note

VHD_1_1_3_3A

Message: Signal names, variable names, type names, label names and function names should be at least 2 characters

Description Signal names, variable names, type names, label names, and function names should be at least 2 characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_3_3B

Message: Signal names, variable names, type names, label names and function names should not exceed 40 characters

Description Signal names, variable names, type names, label names, and function names should not exceed 40 characters.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_1_1_4_1

Message: Use name+'_pac.vhd' for package files

Description Package files should be names in name+'_pac.vhd format.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_4_2A

Message: For constant declarations, names should be upper case only

Description All constants should be declared using upper-case characters only.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_4_2B

Message: For constant declarations, names should start with 'C_' or 'P_'

Description Constants declared should start with 'C_' or 'P_'.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_4_6

Message: Do not propagate constants through ports

Description Avoid propagating constants through ports.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Error

VHD_1_1_4_7

Message: Hard-coded value for bus size is not recommended

Description Bus width should not be hard-coded.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_4_9

Message: Do not use generic at top level

Description Generic cannot be used at the top level.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Error

VHD_1_1_5_1A

Message: Register name should end with _reg, _REG

Description Register name should end with _reg or _REG.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_5_1B

Message: Register name should include the driving clock name

Description Register name should include the driving clock name.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_5_2A

Message: Clock names should use CK or CLK, plus up to 3 extra characters when multiple clocks exist

Description Name the clock signals as CK or CLK. When multiple clocks exist, use extra characters not exceeding 3 characters (for example, CLK0, CLK_IN, CLK_CPU).For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_5_2B

Message: Reset names should use RST, plus up to 3 extra characters when multiple resets exist

Description Reset names should use RST.When multiple resets exist, use extra characters not exceeding 3 characters (for example, RST0, RST_IN, RST_CPU).For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_6_1

Message: Architecture names should be RTL, BEH, SIM(TB)

Description Architecture names in RTL description should be RTL, and that of behavioral description should be BEH and that of a test bench should be SIM or TB.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Warning

VHD_1_1_6_4

Message: Entity and architecture should be in the same file

Description Entity and architecture descriptions should be in the same file.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_1_NAMING_CONVENTIONS
Language VHDL
Type Block-level
Severity Error

S_1_2_SYNCHRONOUS_DESIGN Ruleset

The following rules are from the S_1_2_SYNCHRONOUS_DESIGN ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_1_2_1_1A

Message: Avoid using multiple clocks in your design

Description Avoid using multiple clocks in your design. Use a single clock in your design as far as possible.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_2_SYNCHRONOUS_DESIGN
Language VHDL
Type Chip-level
Severity Error

VHD_1_2_1_1B

Message: Avoid using both positive-edge and negative-edge triggered flip-flops in your design

Description Avoid using both positive-edge and negative-edge triggered flip-flops in your design. Use a single edge in your design as far as possible.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_2_SYNCHRONOUS_DESIGN
Language VHDL
Type Chip-level
Severity Error

VHD_1_2_1_3

Message: Asynchronous feedback loop detected

Description Asynchronous feedback loop detected. Avoid using feedback in combinational circuits.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_2_SYNCHRONOUS_DESIGN
Language VHDL
Type Chip-level
Severity Fatal

S_1_3_INITIAL_RESET Ruleset

The following rules are from the S_1_3_INITIAL_RESET ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_1_3_1_2

Message: Use asynchronous reset/set/load for initial reset to register

Description Use asynchronous reset/set/load for initial reset to a register.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_3_INITIAL_RESET
Language VHDL
Type Block-level
Severity Warning

VHD_1_3_1_3

Message: Do not use asynchronous set or reset pins for anything other than initial reset

Description Use asynchronous set or reset pins for initial reset only.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_3_INITIAL_RESET
Language VHDL
Type Chip-level
Severity Error

This rule is an instantiation of the DESIGN policy rule NTL_RST05. To change the severity of this rule, you must change the severity of its parent rule NTL_RST05.

VHD_1_3_1_4

Message: Synchronous reset/set/load <%item> detected. Make sure that it has its own hierarchy

Description When using synchronous reset/set/load, make sure that it has its own hierarchy.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_3_INITIAL_RESET
Language VHDL
Type Block-level
Severity Note

VHD_1_3_1_5

Message: Do not use sync_set_reset attribute

Description Avoid using attribute 'sync_set_reset'. Only Design Compiler support it.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_3_INITIAL_RESET
Language VHDL
Type Block-level
Severity Warning

VHD_1_3_1_6

Message: The same signal should not be used as both asynchronous reset/set/load and synchronous reset/set/load

Description Avoid using the same reset/set/load signal as both asynchronous and synchronous reset/set/load.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_3_INITIAL_RESET
Language VHDL
Type Chip-level
Severity Fatal

VHD_1_3_1_7

Message: Do not use asynchronous reset and asynchronous set in same process statement

Description Avoid using asynchronous reset and asynchronous set in the same process block.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_3_INITIAL_RESET
Language VHDL
Type Block-level
Severity Error

VHD_1_3_2_1

Message: No gated reset/set/load except in reset generator GENRST

Description Avoid using logical operands in reset line.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_3_INITIAL_RESET
Language VHDL
Type Chip-level
Severity Error

VHD_1_3_2_2

Message: Internally generated asynchronous reset/set/load <%item> detected

Description Avoid connecting signals other than initial reset signal to the asynchronous reset pins.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_3_INITIAL_RESET
Language VHDL
Type Chip-level
Severity Error

S_1_4_CLOCKS Ruleset

The following rules are from the S_1_4_CLOCKS ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_1_4_1_1

Message: Use gated clocks only in GENCLK block

Description Use gated clocks only in GENCLK block. Creating a clock generation module and supplying clocks from a single clock generation module helps in managing clock distribution efficiently.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_4_CLOCKS
Language VHDL
Type Chip-level
Severity Error

VHD_1_4_2_1

Message: Do not add buffer on clock trees

Description Addition of buffers on clock trees is not recommended.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_4_CLOCKS
Language VHDL
Type Chip-level
Severity Note

VHD_1_4_3_2

Message: Internally generated clock <%item> detected

Description Internally generated clock detected. Connecting an output of a flip-flop to the clock of another flip-flop should be avoided.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_4_CLOCKS
Language VHDL
Type Chip-level
Severity Error

VHD_1_4_3_4

Message: Do not use clock as data

Description Connecting clock signal to any input pins of flip-flop except for clock pin should be strictly avoided.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_4_CLOCKS
Language VHDL
Type Chip-level
Severity Error

VHD_1_4_3_6

Message: Do not use negative edge flipflop

Description Avoid using flip-flops that work on the negative edge.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_4_CLOCKS
Language VHDL
Type Block-level
Severity Error

VHD_1_4_4_1

Message: Do not use multiple clocks in a unit

Description Try to break the design into sub blocks based on the clock they operate upon. Avoid using multiple clocks in a module.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_4_CLOCKS
Language VHDL
Type Block-level
Severity Note

S_1_5_ASYNCHRONOUS_CIRCUITS Ruleset

The following rule is from the S_1_5_ASYNCHRONOUS_CIRCUITS ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_1_5_1_1

Message: To avoid metastability, do not place logic between asynchronous clocks

Description Placing logic between asynchronous clocks can cause metastability problems.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_5_ASYNCHRONOUS_CIRCUITS
Language VHDL
Type Chip-level
Severity Fatal

S_1_6_HIERARCHICAL_DESIGN Ruleset

The following rules are from the S_1_6_HIERARCHICAL_DESIGN ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_1_6_1_1

Message: Limit gate size of a single level to 10,000 gates

Description Always limit gate size of a single level to 10,000 gates to ensure safety.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_6_HIERARCHICAL_DESIGN
Language VHDL
Type Chip-level
Severity Warning

This rule is an instantiation of the DESIGN policy rule NTL_STR99. To change the severity of this rule, you must change the severity of its parent rule NTL_STR99.

VHD_1_6_1_2

Message: Hierarchy should contain 2,000-10,000 gates

Description Hierarchy should contain 2,000-10,000 gates.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_6_HIERARCHICAL_DESIGN
Language VHDL
Type Chip-level
Severity Error

This rule is an instantiation of the DESIGN policy rule NTL_STR100. To change the severity of this rule, you must change the severity of its parent rule NTL_STR100.

VHD_1_6_2_1A

Message: Top level output ports should be registered: %s

Description Output ports at top level should always be registered.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_6_HIERARCHICAL_DESIGN
Language VHDL
Type Chip-level
Severity Warning

VHD_1_6_2_1B

Message: Output ports should be registered

Description Output ports should be registered.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_6_HIERARCHICAL_DESIGN
Language VHDL
Type Block-level
Severity Note

VHD_1_6_4_1

Message: Do not include glue logic at top level

Description The interconnection of basic blocks should not include any glue logic.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_6_HIERARCHICAL_DESIGN
Language VHDL
Type Chip-level
Severity Fatal

VHD_1_6_4_3

Message: Number of I/O ports should not exceed 200. This entity has <%value> ports

Description The maximum number of I/O ports that can be specified is 200.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_1_6_HIERARCHICAL_DESIGN
Language VHDL
Type Block-level
Severity Warning

S_2_1_VHDL_LIMITATIONS Ruleset

The following rules are from the S_2_1_VHDL_LIMITATIONS ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_1_1_1

Message: Use IEEE.std_logic_1164

Description Use standard package IEEE.std_logic_1164.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_1_3

Message: IEEE.numeric_std detected, make sure not to use std_logic_unsigned or std_logic_arith with

Description When IEEE.numeric_std is used, make sure you don't use std_logic_unsigned or std_logic_arith.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Warning

VHD_2_1_2_1

Message: Use only std_logic, std_logic_vector for I/O ports

Description I/O ports in RTL descriptions should be declared using std_logic or std_logic_vector data types only.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_2_2

Message: Use std_logic, std_logic_vector, integer, boolean, unsigned, signed inside an architecture

Description Inside an architecture, use std_logic, std_logic_vector, integer, boolean, unsigned, and signed data type.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_2_3

Message: Specify range when using integer

Description Always specify range when integer is used.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_2_4

Message: Do not use bit or bit_vector

Description Avoid using bit or bit_vector data type.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_2_5

Message: Do not use attribute enum_encoding

Description Avoid using the attribute enum_encoding. Only Design Compiler can understand it.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_2_6

Message: std_logic_vector in port declaration should have range

Description Signals declared with data type std_logic_vector should specify range.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_3_2

Message: Do not use buffer or linkage

Description Avoid using buffer or linkage as port mode. Use only in, out and inout.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_3_3

Message: Do not omit the description of port mode (in, out, inout, buffer, linkage)

Description Description of port mode should not be omitted.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_3_4

Message: Do not assign initial value to input port

Description Avoid assigning initial values to input ports.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_4_3

Message: Do not use shift functions such as sll

Description Do not use shift functions such as sll and srl. Some logic synthesis tools does not support them.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_5_1

Message: Conditional signal assignment statement (when...else) should not exceed 5 levels

Description Nesting of conditional signal assignment statement 'when-else' should not exceed 5 levels.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_6_1

Message: Specification of array should be [MSB:LSB]

Description When an array is specified it should be in the format of [MSB downto LSB]. For example:
DATABUS : in std_logic_vector (7 downto 0.
For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Warning

VHD_2_1_6_2

Message: LSB of an array should be zero whenever possible

Description LSB of an array must be zero.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Warning

VHD_2_1_6_3

Message: Do not use operators in index of array

Description Avoid using operators in index of array. Use simple signal names as array indexes to improve readability of code.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Warning

VHD_2_1_6_4

Message: Possible range overflow

Description The range of an array should be specified correctly.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Warning

VHD_2_1_7_3

Message: Do not mix bit position specification and others in a concatenation

Description Avoid mixing bit position specification and others construct in a concatenation operation. Some simulators will interpret as syntax error.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Note

VHD_2_1_8_5

Message: Do not use recursion call in function statement

Description Avoid recursion call in function statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_8_8

Message: Do not use procedures

Description Avoid using procedure in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_8_9

Message: Use fully assign variables in subprogram

Description Mention all possible status for assignments to the return type in function specification.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_8_10

Message: Always end function specification with return

Description Functions should always terminate with a return statement. Statements appearing after the return statement are not executed.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Warning

VHD_2_1_9_4

Message: Use only the following attributes: range, length, left, right, high, low, reverse_range, and event

Description Always use only the following attributes namely range, length, left, right, high, low, reverse_range, and event.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_10_1

Message: Do not use block statement

Description Using block statement in RTL description is strictly prohibited.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_10_2

Message: Do not use record type

Description Using record type in RTL description is strictly prohibited.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_10_3

Message: Do not use shared variable

Description Using shared variables in RTL description is strictly prohibited.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_10_4

Message: Do not use while-loop statement

Description Avoid using while-loop statement in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_10_6

Message: Do not use selected signal assignment (with-select)

Description Avoid using with-select statement in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_10_7

Message: Do not use configuration

Description Avoid using configuration in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_10_8

Message: Do not use synopsys attributes

Description Do not use synopsys attributes. This may create problems when using different synthesis tools.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Warning

VHD_2_1_10_9

Message: Do not use access type

Description Avoid using access type in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_10_10

Message: Do not use alias declaration

Description Avoid declaring alias in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_10_11

Message: Do not use bus, register

Description Avoid using bus, register in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Error

VHD_2_1_10_12

Message: Do not use disconnect

Description Avoid using disconnect in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

VHD_2_1_10_13

Message: Do not use multiple waveforms in signal assignment

Description Avoid using multiple waveforms in signal assignment.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_1_VHDL_LIMITATIONS
Language VHDL
Type Block-level
Severity Fatal

S_2_2_PROCESS_FOR_COMBINATIONAL Ruleset

The following rules are from the S_2_2_PROCESS_FOR_COMBINATIONAL ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_2_2_1

Message: Missing signals in sensitivity list of combinational process statements

Description Specify all the signals that appear in the RHS of assignment statements and conditional expressions in sensitivity list of combinational process block.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_2_PROCESS_FOR_COMBINATIONAL
Language VHDL
Type Block-level
Severity Fatal

VHD_2_2_2_2

Message: Redundant signals in sensitivity list of combinational process statements

Description Avoid redundant signals in sensitivity list of combinational process statements.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_2_PROCESS_FOR_COMBINATIONAL
Language VHDL
Type Block-level
Severity Warning

VHD_2_2_2_3

Message: Do not use wait statements in process statements

Description Wait statement should not be used in process statements. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_2_PROCESS_FOR_COMBINATIONAL
Language VHDL
Type Block-level
Severity Fatal

S_2_3_FF_INFERENCE Ruleset

The following rules are from the S_2_3_FF_INFERENCE ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_3_1_1

Message: Use signal assignment statement in the flip-flop inference. Do not use variable assignment

Description To infer flip-flop, use signal assignment statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Fatal

VHD_2_3_1_3

Message: Insertion of delay expressions in assignments that infer flip-flops is recommended

Description To avoid race conditions, insert delay values in assignments that infer flip-flops.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Warning

VHD_2_3_1_4

Message: Use of delay values in assignments other than those that infer flip-flops is not recommended

Description To avoid race conditions, use delay values only in assignment expressions for signals inferring flip-flops.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Error

VHD_2_3_1_5

Message: Use positive integers for delay values in assignments that infer flip-flops

Description Use only positive integers to specify delay values in assignments that infer flip-flops.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Fatal

VHD_2_3_1_6

Message: Use positive integers for delay values in assignments

Description This rule fires when there is negative integer delay value in assignment.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Fatal

The following example illustrates this rule:

library IEEE;
use ieee.std_logic_1164.all;

entity test is
end entity;

architecture arch of test is

function real_val return real is
       variable X : real;
  begin
       X := 3.14;
       return X;
  end function real_val ;
signal Y : real;
begin
	Y <= real_val;
	process(Y)
	begin	
	     Y <= 4.0 after -10ns;
	end process;
end arch;

VHD_2_3_1_7

Message: Do not use multiple asynchronous resets or multiple asynchronous sets in an always block
Description Leda flags this rule when multiple asynchronous resets/sets is used in a process statement. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Fatal

VHD_2_3_1_8

Message: Do not use wait statements in descriptions of clock events

Description When describing clock events, avoid using wait statements.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Fatal

VHD_2_3_1_9

Message: Do not use rising_edge and falling_edge functions

Description Do not mix both rising edge and falling edge of flip-flop inference.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Note

VHD_2_3_2_2

Message: Do not use variables in process statements

Description Avoid using variables in process statements.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Error

VHD_2_3_3_1

Message: Do not use clock with multiple different edges in a process statement

Description Avoid using multiple different clock edges in a process statement. They are not synthesizable.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Fatal

VHD_2_3_4_1

Message: Do not initialize flip-flops in signal declaration, port declaration, variable declaration

Description Initializing flip-flops in signal declaration, port declaration, and variable declaration is not permitted.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Fatal

VHD_2_3_5_1

Message: Flip-flop inputs should not be constants

Description Avoid descriptions that generate flip-flops having fixed input value.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Chip-level
Severity Error

VHD_2_3_6_1

Message: Do not mix flip-flop with and without asynchronous reset/set/load in the same process statement

Description Avoid mixing flipflop with asynchronous reset/set/load and without in the same process statement. Such coding styles are misleading and debugging is very difficult.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Error

VHD_2_3_6_2

Message: Asynchronous reset/set/load signals must be active low

Description Asynchronous reset/set/load signals should be active low.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_3_FF_INFERENCE
Language VHDL
Type Block-level
Severity Warning

S_2_4_LATCH_INFERENCE Ruleset

The following rules are from the S_2_4_LATCH_INFERENCE ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_4_1_2

Message: Latch inferred, make sure that it has its own hierarchy

Description To avoid synthesis tool generating unintentional gated clock circuit because of incomplete if statements, latches should be have their own hierarchy.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_4_LATCH_INFERENCE
Language VHDL
Type Block-level
Severity Warning

VHD_2_4_1_3

Message: Latch inferred, make sure that this latch does not have any asynchronous reset/set/load

Description Avoid usage of latches having asynchronous reset/set/load. This is because latch inference depends on the synthesis tool used. This is not reliable because not many ASIC vendor libraries have such latches.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_4_LATCH_INFERENCE
Language VHDL
Type Block-level
Severity Error

VHD_2_4_1_5

Message: Latch enabled by a clock feeds latches enabled by the same clock

Description Latch enabled by a clock should feed another latch enabled by a different clock.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_4_LATCH_INFERENCE
Language VHDL
Type Chip-level
Severity Error

S_2_5_TRISTATE_BUFFERS Ruleset

The following rules are from the S_2_5_TRISTATE_BUFFERS ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_5_1_1

Message: Tristate detected; make sure that it has its own hierarchy

Description Always tristate buffers should be made as a separate block.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_5_TRISTATE_BUFFERS
Language VHDL
Type Block-level
Severity Warning

VHD_2_5_1_2

Message: Do not use logic in conditional expression to infer tristate

Description Avoid using logics in conditional statements to infer tristate. This may lead to malfunctioning or increased power consumption.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_5_TRISTATE_BUFFERS
Language VHDL
Type Chip-level
Severity Warning

This rule is an instantiation of the DESIGN policy rule NTL_STR37. To change the severity of this rule, you must change the severity of its parent rule NTL_STR37.

VHD_2_5_1_4

Message: Tristate buffers connection should not exceed more than 5

Description Output drivers connected to tristate buffers should be 5 or less.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_5_TRISTATE_BUFFERS
Language VHDL
Type Block-level
Severity Warning

VHD_2_5_1_5

Message: Do not use multiple drivers except for tristate

Description Generally, to strengthen the drive capacity of output, cells of BUF, INV are added simultaneously to the net. Such connections are recommended to be done on layout and describing to connect two or more output drivers other than tristate buffers in RTL should be avoided.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_5_TRISTATE_BUFFERS
Language VHDL
Type Chip-level
Severity Fatal

VHD_2_5_1_6

Message: Inout should not be directly connected to output

Description Make sure an inout signal connection is not connected directly to an input/output signal.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_5_TRISTATE_BUFFERS
Language VHDL
Type Block-level
Severity Fatal

S_2_6_PROCESS_STATEMENT_DESCRIPTION Ruleset

The following rules are from the S_2_6_PROCESS_STATEMENT_DESCRIPTION ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_6_1_3

Message: Output signals from process statement should not exceed 5

Description Specify five or less output signals in process statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_6_PROCESS_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

VHD_2_6_1_4

Message: The number of lines in process statements should not exceed 200

Description The total number of lines inside a process statement should be less than 200.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_6_PROCESS_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

VHD_2_6_2_1A

Message: Do not use multiple if statements in the same process statement

Description Avoid including description of more than one if statement inside a process statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_6_PROCESS_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

VHD_2_6_2_1B

Message: Do not use multiple case statements in the same process statement

Description Avoid including description of more than one case statement inside a process statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_6_PROCESS_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

S_2_7_IF_STATEMENT_DESCRIPTION Ruleset

The following rules are from the S_2_7_IF_STATEMENT_DESCRIPTION ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_7_1_3

Message: If statement in combinational circuit should end with else (not with else if)

Description To avoid unintentional latch inference, make sure if statements in combinational circuits end with an else clause.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_7_IF_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Error

VHD_2_7_3_1

Message: Number of nested elements in if_statement should be 5 or less

Description The number of levels in any if statement should not exceed 5.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_7_IF_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

S_2_8_CASE_STATEMENT_DESCRIPTION Ruleset

The following rules are from the S_2_8_CASE_STATEMENT_DESCRIPTION ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_8_1_4

Message: Always add 'others' clause in case statement

Description Any case statement should have 'others' clause. This is necessary, so that if none of the values match, the default clause is executed. Otherwise, none of the statements inside a case statement is executed.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_8_CASE_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

VHD_2_8_1_5

Message: Do not use '-', 'X' values in choice of case statement

Description Don't care value 'x' and unknown value 'z' cannot be used as a choice in case statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_8_CASE_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Note

VHD_2_8_2_2

Message: Number of case alternatives should be less than 100

Description The number of case items present in a case statement should mot exceed 100.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_8_CASE_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

S_2_9_FOR_STATEMENT_DESCRIPTION Ruleset

The following rules are from the S_2_9_FOR_STATEMENT_DESCRIPTION ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_9_1_1

Message: Do not use for loop statement to generate parity circuit

Description Use for statements only for simple repeating statements.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_9_FOR_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

VHD_2_9_3_1A

Message: Do not use next statement in for-loop statement

Description Avoid using next statement inside a for-loop statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_9_FOR_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

VHD_2_9_3_1B

Message: Do not use exit statement in for-loop statement

Description Avoid using exit statement inside a for-loop statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_9_FOR_STATEMENT_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

S_2_10_OPERATOR_DESCRIPTION Ruleset

The following rules are from the S_2_10_OPERATOR_DESCRIPTION ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_10_1_3

Message: Do not compare with 'X', 'Z', 'U', '-', 'W', 'H' or 'L' (ex. if(A=XX))

Description Comparison of values with 'X', 'Z', 'U', '-', 'W', 'H', 'L' is not allowed. This results in simulation and synthesis mismatch.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Error

VHD_2_10_1_4

Message: Do not assign 'X' except for the default clause of case statements

Description Assign 'x' only in the others clause of a case statement.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

VHD_2_10_1_5

Message: Do not use values including 'X', 'Z', 'U', '-', 'W', 'H' or 'L' (ex. if(A=1X1))

Description Avoid using values including 'X', 'Z', 'U', '-', 'W', 'H', and 'L'.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

VHD_2_10_3_1

Message: Operand size mismatch in relational operator

Description Operand size in relational operators should match.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

VHD_2_10_4_3

Message: Do not use conv_std_logic_vector function to convert integer to std_logic_vector

Description Avoid using conv_std_logic_vector function to convert integer to std_logic_vector.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Error

VHD_2_10_4_8

Message: Do not use To_stdlogicvector function in VHDL93

Description Use std_logic_vector( conv_unsigned( , ) ) function to convert integer to std_logic_vector. Do not use To_stdlogicvector( ) function in VHDL93.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Error

VHD_2_10_6_6

Message: Do not use '/', 'mod', 'rem', '**', 'abs' in assignments

Description Avoid using operators like '/', 'mod', 'rem', and '**' in assignment statements.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Fatal

VHD_2_10_6_7

Message: Do not use more than one arithmetic operator in one line

Description Always mention single arithmetic operator in a line.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

VHD_2_10_7_1

Message: Do not use arithmetic operations in the conditional expressions of if statements

Description The conditional expression in if statement should not have arithmetic operation.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_10_OPERATOR_DESCRIPTION
Language VHDL
Type Block-level
Severity Error

S_2_11_STATE_MACHINE_DESCRIPTION Ruleset

The following rules are from the S_2_11_STATE_MACHINE_DESCRIPTION ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_2_11_1_1

Message: Moore style is recommended for FSM

Description Moore type state machine is recommended because it is considered to be a safe state machine from timing perspective.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_11_STATE_MACHINE_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

VHD_2_11_1_3

Message: Define FSM state value by using parameters

Description Define FSM state value using parameter construct for improved readability.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_11_STATE_MACHINE_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

VHD_2_11_1_4

Message: Number of states in FSM should not exceed 40

Description Maintain the number of states in FSM less than 40 when using binary coding or grey coding.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_11_STATE_MACHINE_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

VHD_2_11_2_1

Message: Create a separate hierarchy for FSM

Description Create FSM as an independent block as far as possible.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_11_STATE_MACHINE_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

VHD_2_11_3_1

Message: Separate the flip-flop statements and state machine description case statements in the FSM

Description The state machine should be described in such a way that the combinational part describing the state and the sequential part are separated.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_2_11_STATE_MACHINE_DESCRIPTION
Language VHDL
Type Block-level
Severity Warning

S_3_1_CREATE_FUNCTION_LIBRARIES Ruleset

The following rules are from the S_3_1_CREATE_FUNCTION_LIBRARIES ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_3_1_2_7

Message: Do not use embedded dc_shell scripts in the source code

Description Never use the embedded dc_shell scripts in the source code.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_1_CREATE_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Fatal

VHD_3_1_3_1

Message: Port ordering should be the same between the component and its instantiation

Description Port ordering should be uniform and same between the component and its instantiation.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_1_CREATE_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Warning

VHD_3_1_3_2

Message: Port description order should be the following: in, out, inout

Description Put port descriptions in the following order: in, out, and inout.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_1_CREATE_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Warning

VHD_3_1_3_4A

Message: Define one signal per line in each declaration

Description Always declare only one signal in a line.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_1_CREATE_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Warning

VHD_3_1_3_4B

Message: Always add comments in each line of declaration

Description Add enough comments in each line of declaration.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_1_CREATE_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Warning

VHD_3_1_4_4

Message: Do not use multiple statements in one line

Description Single expression in one line is recommended. This makes the code easier to read.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_1_CREATE_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Warning

VHD_3_1_4_5

Message: The number of characters in 1 line should not exceed 110 (Line <%value>)

Description The number of characters in a line should not exceed 110.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_1_CREATE_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Warning

VHD_3_1_5_2

Message: Specify bit width using generic declaration

Description Bit width information should be specified using generic declaration.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_1_CREATE_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Note

S_3_2_USING_FUNCTION_LIBRARIES Ruleset

The following rules are from the S_3_2_USING_FUNCTION_LIBRARIES ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_3_2_2_1

Message: Use constant declaration to define constant value, except numeric values of 0-7 and vector values of all 0 and all 1

Description Define constants as parameters except for numeric values of 0-7 and vector values of all 0 and 1. This makes debugging easier.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_2_USING_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Warning

VHD_3_2_3_1

Message: Component instantiation must be done by name. Instantiating by position can cause errors.

Description While instantiating components, connect the ports by name and not by position. This facilitates easier understanding of port connections.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_2_USING_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Fatal

VHD_3_2_3_3

Message: Do not use direct instantiation, even though this has been supported since VHDL'93

Description Avoid using direct instantiation.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_2_USING_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Fatal

VHD_3_2_4_1

Message: Use only integer for generic declaration

Description Only integers should be used for generic declaration in RTL description.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_2_USING_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Fatal

VHD_3_2_4_3

Message: Specify formal parameter when writing generic in component instantiation

Description Formal parameters have to be specified when writing generic in component instantiation.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_2_USING_FUNCTION_LIBRARIES
Language VHDL
Type Block-level
Severity Error

S_3_3_TEST_FACILITATION_DESIGN Ruleset

The following rules are from the S_3_3_TEST_FACILITATION_DESIGN ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_3_3_1_1

Message: Make internal clocks controllable from external pins

Description Clocks should be controllable from external input ports.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_3_TEST_FACILITATION_DESIGN
Language VHDL
Type Chip-level
Severity Fatal

VHD_3_3_1_3

Message: The output of random logic should not be used as a clock

Description Avoid using an output of random logic as a clock.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_3_TEST_FACILITATION_DESIGN
Language VHDL
Type Chip-level
Severity Error

This rule is an instantiation of the DESIGN policy rule NTL_CLK12. To change the severity of this rule, you must change the severity of its parent rule NTL_CLK12.

VHD_3_3_1_4

Message: Asynchronous reset/set/load <%item> must be directly controllable from external input port

Description An external input port should be able to control asynchronous reset/set/load of any flip-flop.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_3_TEST_FACILITATION_DESIGN
Language VHDL
Type Chip-level
Severity Fatal

VHD_3_3_3_1

Message: A clock must not be connected to the D input of a flipflop

Description Clock signal must not be connected as input to D flip-flop.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_3_TEST_FACILITATION_DESIGN
Language VHDL
Type Chip-level
Severity Fatal

This rule is an instantiation of the DESIGN policy rule NTL_STR61. To change the severity of this rule, you must change the severity of its parent rule NTL_STR61.

VHD_3_3_3_2

Message: VDD or GND should not be connected to the D input of a flip-flop

Description Do not connect VCC or GND to the D input of a flip-flop.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_3_TEST_FACILITATION_DESIGN
Language VHDL
Type Chip-level
Severity Warning

This rule is an instantiation of the DESIGN policy rule NTL_DFT41. To change the severity of this rule, you must change the severity of its parent rule NTL_DFT41.

VHD_3_3_6_2

Message: Do not mix clock and reset lines

Description Avoid mixing clock and reset lines.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_3_TEST_FACILITATION_DESIGN
Language VHDL
Type Chip-level
Severity Fatal

This rule is an instantiation of the DESIGN policy rule NTL_STR18. To change the severity of this rule, you must change the severity of its parent rule NTL_STR18.

VHD_3_3_6_3

Message: A flipflop output must not be directly connected to an asynchronous set or reset

Description Do not connect a flip-flop output directly to an asynchronous set or reset.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_3_TEST_FACILITATION_DESIGN
Language VHDL
Type Chip-level
Severity Fatal

This rule is an instantiation of the DESIGN policy rule NTL_RST06. To change the severity of this rule, you must change the severity of its parent rule NTL_RST06.

VHD_3_3_8_2

Message: Tristate enable signals should be controllable from outside

Description Tristate enable signals should be controllable from outside.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VER_STARC_2002
Ruleset S_3_3_TEST_FACILITATION_DESIGN
Language Verilog
Type Chip-level
Severity Warning

This rule is an instantiation of the DESIGN policy rule NTL_STR54. To change the severity of this rule, you must change the severity of its parent rule NTL_STR54.

S_3_4_LOW_POWER

The following rules are from the S_3_4_LOW_POWER ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_3_4_1_1

Message: Gated clocks can only be used at the top level

Description Gated clocks can be used only at the top level.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VER_STARC_2002
Ruleset S_3_5_DESIGN_MANAGEMENT
Language Verilog
Type Chip-level
Severity Fatal

This rule is an instantiation of the DESIGN policy rule NTL_CLK18. To change the severity of this rule, you must change the severity of its parent rule NTL_CLK18.

S_3_5_DESIGN_MANAGEMENT Ruleset

The following rules are from the S_3_5_DESIGN_MANAGEMENT ruleset. For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:

VHD_3_5_3_1

Message: Use header comments for each entity declaration

Description Header comments must be present for each entity declaration.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_5_DESIGN_MANAGEMENT
Language VHDL
Type Block-level
Severity Error

VHD_3_5_3_1A

Message: Indicate the 'FILE NAME' in the header

Description Header must contain the file name information.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_5_DESIGN_MANAGEMENT
Language VHDL
Type Block-level
Severity Warning

VHD_3_5_3_1B

Message: Indicate the 'TYPE' in the header

Description Header must contain the type information.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_5_DESIGN_MANAGEMENT
Language VHDL
Type Block-level
Severity Warning

VHD_3_5_3_1C

Message: Indicate the 'FUNCTION' in the header

Description Circuit function must be defined in the header.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_5_DESIGN_MANAGEMENT
Language VHDL
Type Block-level
Severity Warning

VHD_3_5_3_1D

Message: Indicate the 'edit' in the header

Description Header must contain the editor information.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_5_DESIGN_MANAGEMENT
Language VHDL
Type Block-level
Severity Warning

VHD_3_5_3_1E

Message: Indicate the 'Author' in the header

Description Author of the module must be mentioned in the header.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_5_DESIGN_MANAGEMENT
Language VHDL
Type Block-level
Severity Warning

VHD_3_5_3_1F

Message: Indicate the 'Date' in the header

Description Module creation date must be present in the header.For more information, see the Japanese or English language version of the STARC Design Style Guide (DSG) Coding Guidelines for VHDL in the $LEDA_PATH/doc/STARC directory:
Policy VHD_STARC_DSG
Ruleset S_3_5_DESIGN_MANAGEMENT
Language VHDL
Type Block-level
Severity Warning