1
IEEE VHDL Coding Rules

Introduction

This chapter provides detailed reference information for the VHDL IEEE_RTL_SYNTH_SUBSET policy for the Leda Checker tool. This policy contains rules defining the most common synthesis subsets for Register Transfer Level (RTL) synthesis. They are based on industrial subsets and on the rules featured in Chapter 8 of the following document:

IEEE 1076.6 "Draft Standard for VHDL Register Transfer Level Synthesis"

The rules are grouped into rulesets. Each ruleset imposes constraints on the elements of the language.for a given chapter of the VHDL Language Reference Manual (LRM) and is derived from the corresponding subsection in Chapter 8 of the IEEE 1076.6 draft document. Table 2 provides an overview of the different IEEE_RTL_SYNTH_SUBSET policy rulesets for VHDL.
Table 2: IEEE_VHDL Policy Rulesets 
Ruleset
Descriptions
"Design Entities Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 1 of the VHDL LRM.
"Packages Subprograms Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 2 of the VHDL LRM.
"Types Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 3 of the VHDL LRM.
"Declarations Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 4 of the VHDL LRM.
"Specifications Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 5 of the VHDL LRM.
"Names Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 6 of the VHDL LRM.
"Expressions Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 7 of the VHDL LRM.
"Sequential Statements Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 8 of the VHDL LRM.
"Concurrent Statements Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 9 of the VHDL LRM.
"Lexical Elements Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of Chapter 13 of the VHDL LRM.
"Language Environment Ruleset" This is a set of rules implementing the constraints imposed by synthesis on elements of chapter 14 of the VHDL LRM.

Design Entities Ruleset

The following rules are from the design entities ruleset:

SYN1_1_1_A

Message: Process statements are ignored in entities

Description An entity can only contains passive statements used for simulation.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Warning

SYN1_1_1_B

Message: Procedure call statements are ignored in entities

Description An entity can only contains passive statements used for simulation.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Warning

SYN1_1_1_C

Message: Assertion statements are ignored in entities

Description An entity can only contains passive statements used for simulation.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Warning

SYN1_1_2

Message: Port default values are ignored

Description Default port values are ignored by synthesis tools because they may cause differences between pre- and post-synthesis simulation results.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Warning

SYN1_1_2_1_A

Message: Group declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_B

Message: Use clauses are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error.

SYN1_1_2_1_C

Message: Disconnection specifications are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_D

Message: Attribute specifications are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_E

Message: Signal declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_F

Message: Attribute declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_G

Message: Group template declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_H

Message: Shared variable declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_I

Message: Constant declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_J

Message: Subtype declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_K

Message: Type declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_L

Message: Subprogram declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_M

Message: File declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_2_1_N

Message: Alias declarations are illegal in entities

Description Reduces reusability, increases recompilation time.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_1_3

Message: Only generics of type integer are accepted

Description Synthesis tools transform all generics to type integer.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Warning

SYN1_2_1_1_A

Message: File declarations are illegal in architectures

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_2_1_1_B

Message: Disconnection specifications are ignored in architectures

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Warning

SYN1_2_1_1_C

Message: Attribute specifications are ignored in architectures

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Warning

SYN1_2_1_1_D

Message: Alias declarations are ignored in architectures

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Warning

SYN1_2_1_1_E

Message: Group declarations are illegal in architectures

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_2_1_1_F

Message: Shared variable declarations are illegal in architectures

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_2_1_1_G

Message: Group template declarations are illegal in architectures

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_2_1_2

Message: Use clauses can only indicate package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_3_1_A

Message: Group declarations are illegal in configuration declarations

Description Most synthesis tools only allow default configurations for component instantiations. This means a configuration declaration only needs to configure the top-level architecture.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_3_1_B

Message: Use clauses are illegal in configuration declarations

Description Most synthesis tools only allow default configurations for component instantiations. This means a configuration declaration only needs to configure the top-level architecture
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_3_1_C

Message: Attribute specifications are illegal in configuration declarations

Description Most synthesis tools only allow default configurations for component instantiations. This means a configuration declaration only needs to configure the top-level architecture
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_3_2

Message: Component configurations are illegal in block configurations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_3_3

Message: Use clauses are illegal in block configurations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_3_4_A

Message: Block statement labels are illegal in block configurations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

SYN1_3_4_B

Message: Generate statement labels are illegal in block configurations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DESIGN_ENTITIES
Language VHDL
Type Block-level
Severity Error

Packages Subprograms Ruleset

The following rules are from the packages subprograms ruleset:

SYN2_1_1

Message: Default values for subprogram parameters are ignored

Description Ignored by synthesis tools. May cause pre- and post-synthesis simulation results to differ.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Warning

SYN2_1_2

Message: Impure subprograms are not allowed

Description Most synthesis tools do not support VHDL93.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_1_3

Message: Pure keyword cannot be used

Description Most synthesis tools do not support VHDL93.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_2_1_A

Message: File declarations are illegal in subprograms

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_2_1_B

Message: Group template declarations are illegal in subprograms

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_2_1_C

Message: Group declarations are illegal in subprograms

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_2_1_D

Message: Alias declarations are ignored in subprograms

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Warning

SYN2_2_2

Message: Assertion statements are ignored in subprogram bodies

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Warning

SYN2_2_3

Message: Report statements are ignored in subprogram bodies

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Warning

SYN2_2_4

Message: Wait statements not allowed in subprogram bodies

Description Subprograms should only contain combinatorial logic.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_2_5

Message: Recursion is illegal unless bounded by a static value

Description Allows unrolling for optimization.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_2_6

Message: Use clauses can only indicate package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_5_1

Message: User-defined resolution functions are illegal

Description Most synthesis tools only accept IEEE.STD_LOGIC_1164. Resolved as resolution function.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_5_2_A

Message: File declarations are illegal in package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_5_2_B

Message: Group declarations are illegal in package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_5_2_C

Message: Alias declarations are ignored in package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Warning

SYN2_5_2_D

Message: Disconnection specifications are ignored in package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Warning

SYN2_5_2_E

Message: Shared variable declarations are illegal in package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_5_2_F

Message: Global signal declarations in package declaration cannot be used

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_5_2_G

Message: Group template declarations are illegal in package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_5_3

Message: Signal declarations in packages must have default value

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_5_4

Message: Use clauses can only indicate package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_6_1_A

Message: Group template declarations are illegal in package bodies

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_6_1_B

Message: Shared variable declarations are illegal in package bodies

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_6_1_C

Message: File declarations are illegal in package bodies

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_6_1_D

Message: Group declarations are illegal in package bodies

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

SYN2_6_2

Message: Alias declarations are ignored in package bodies

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Warning

SYN2_6_3

Message: Use clauses can only indicate package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset PACKAGES_SUBPROGRAMS
Language VHDL
Type Block-level
Severity Error

Types Ruleset

The following rules are from the types ruleset:

SYN3_1_1

Message: Floating type definitions are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Warning

SYN3_1_2

Message: Physical type definitions are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Warning

SYN3_1_3

Message: Integer value must be in range -(2**31-1) to
(2**31-1)

Description Synthesis tools only support 32-bit arithmetic.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Error

SYN3_1_4

Message: Null ranges are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Error

SYN3_1_5

Message: Predefined type SEVERITY_LEVEL is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Warning

SYN3_1_6

Message: Predefined type STD_FILE_OPEN_KIND is illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Error

SYN3_1_7

Message: Predefined type STD_FILE_OPEN_STATUS is illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Error

SYN3_2_1_A

Message: Multi-dimension arrays are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Error

SYN3_3_1

Message: Access type definitions are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Warning

SYN3_4_1

Message: File type definitions are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset TYPES
Language VHDL
Type Block-level
Severity Error

Declarations Ruleset

The following rules are from the declarations ruleset:

SYN4_1_1_A

Message: Incomplete type declarations are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_1_1_1

Message: Deferred constant declarations are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_3_1_2_1

Message: Initial values for signal declarations are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_1_2_2_A

Message: Bus signal kind is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_1_2_2_B

Message: Register signal kind is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_1_3_1

Message: Initial values for variable declarations are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_1_3_2

Message: Shared variable declarations are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_3_1_4_1

Message: File declarations are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_3_2_1

Message: Buffer mode will be transformed to out mode by synthesis tools

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_2_1_1

Message: Illegal association element in association list

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_3_2_1_2

Message: Actuals of mode in and out cannot be same object

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_3_2_2

Message: Linkage mode is illegal in interface declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_3_2_3

Message: Bus keyword is illegal in interface declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_3_2_4

Message: Default expressions are ignored in interface signal declaration

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_2_5

Message: Default expressions are ignored in interface variable declaration

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_2_6

Message: Interface file declarations are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_3_3_1

Message: Alias declarations are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Warning

SYN4_4_1

Message: User defined attribute declaration is illegal

Description Usually synthesis tools will allow attribute declarations from a special package named ATTRIBUTES. Other user-defined attribute declarations are illegal.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_6_1

Message: Group template declarations are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

SYN4_7_1

Message: Group declarations are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DECLARATIONS
Language VHDL
Type Block-level
Severity Error

Specifications Ruleset

The following rules are from the specifications ruleset:

SYN5_1_1

Message: Others keyword not allowed in attribute specification

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SPECIFICATIONS
Language VHDL
Type Block-level
Severity Error

SYN5_1_2

Message: All keyword not allowed in attribute specification

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SPECIFICATIONS
Language VHDL
Type Block-level
Severity Error

SYN5_2_1

Message: Configuration specifications are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SPECIFICATIONS
Language VHDL
Type Block-level
Severity Warning

SYN5_3_1

Message: Disconnection specifications are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SPECIFICATIONS
Language VHDL
Type Block-level
Severity Warning

Names Ruleset

The following rules are from the names ruleset:

SYN6_6_1

Message: Illegal attribute name

Description Most synthesis tools only support the following predefined attributes BASE, LEFT, RIGHT, LOW, HIGH, LENGTH, RANGE, REVERSE_RANGE, EVENT, STABLE, or attributes declared in a package named ATTRIBUTES.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset NAMES
Language VHDL
Type Block-level
Severity Error

SYN6_6_2

Message: Expressions in attribute names are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset NAMES
Language VHDL
Type Block-level
Severity Error

Expressions Ruleset

The following rules are from the expressions ruleset:

SYN7_2_1

Message: STD.STANDARD.XNOR operator not allowed

Description Added in VHDL93.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language VHDL
Type Block-level
Severity Error

SYN7_2_2

Message: Standard shift operators not allowed

Description Added in VHDL93.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language VHDL
Type Block-level
Severity Error

SYN7_2_6_1_A

Message: RHS of operators /,REM and MOD must be static power of 2

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language VHDL
Type Block-level
Severity Error

SYN7_2_6_1_B

Message: Operators /,REM and MOD must have positive operands

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language VHDL
Type Block-level
Severity Error

SYN7_2_6_1_C

Message: LHS of operator ** must have static value 2

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language VHDL
Type Block-level
Severity Error

SYN7_2_6_1_D

Message: RHS of operator ** must be positive

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language VHDL
Type Block-level
Severity Error

SYN7_3_1_1

Message: Null literals are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language VHDL
Type Block-level
Severity Error

SYN7_3_2_1_1

Message: Record aggregates are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset EXPRESSIONS
Language VHDL
Type Block-level
Severity Error

Sequential Statements Ruleset

The following rules are from the sequential statements ruleset:

SYN8_1_1_A

Message: Labels are not allowed in wait statements

Description Only allowed in VHDL93.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_1_2

Message: Sensitivity clauses are not allowed in wait statements

Description The only wait statements allowed are the following:
wait until clock_signal_name =clock_boolean_value ;
wait until clock_signal_name 'event and 
clock_signal_name =clock_boolean_value ;
wait until clock_signal_name =clock_boolean_value 
and clock_signal_name 'event;
where:
clock_boolean_value is the literal '0' or '1' of 
types BIT,STD_LOGIC or STD_ULOGIC
clock_signal_name is a port declaration.

Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_1_3

Message: Illegal condition in wait_statement

Description The only wait statements allowed are the following:
wait until clock_signal_name =clock_boolean_value ;
wait until clock_signal_name 'event and 
clock_signal_name =clock_boolean_value ;
wait until clock_signal_name =clock_boolean_value 
and clock_signal_name 'event;
where:
clock_boolean_value is the literal '0' or '1' of 
types BIT,STD_LOGIC or STD_ULOGIC
clock_signal_name is a port declaration.

Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_1_4

Message: Timeout clauses are ignored in wait statements

Description The only wait statements allowed are the following:
wait until clock_signal_name =clock_boolean_value ;
wait until clock_signal_name 'event and 
clock_signal_name =clock_boolean_value ;
wait until clock_signal_name =clock_boolean_value 
and clock_signal_name 'event;
where:
clock_boolean_value is the literal '0' or '1' of 
types BIT,STD_LOGIC or STD_ULOGIC
clock_signal_name is a port declaration.

Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN8_2_1

Message: Assertion statements are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN8_2_2

Message: Labels on assertion statements are not supported

Description Only allowed in VHDL93.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_3_1

Message: Report statements are illegal

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_4_1

Message: Multiple waveform elements are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_4_1_1

Message: Null waveforms are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_4_1_2

Message: After expressions in waveforms are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_4_3

Message: Labels on signal assignment statements are not supported

Description Only allowed in VHDL93.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_4_4

Message: Keyword reject is not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_4_5

Message: Keyword inertial is not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_4_6

Message: Unaffected waveforms are not supported

Description Only allowed in VHDL93.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_5_1

Message: Labels on variable assignment statements are not supported

Description VHDL93 modification.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_6_1_B

Message: Labels are not allowed in procedure call statements

Description VHDL93 modification.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_7_1

Message: Labels are not allowed in if statements

Description VHDL93 modification.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_8_1

Message: Labels are not allowed in case statements

Description VHDL93 modification.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_9_1

Message: For loops must have globally static bounds

Description Allows unrolling for synthesis optimization.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_9_2

Message: Wait statements cannot appear inside for loops

Description Facilitates unrolling for synthesis optimization.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_9_3

Message: While loops are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_10_1

Message: Labels are not allowed in next statement

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_11_1

Message: Labels are not allowed in exit statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN8_12_1

Message: Labels are not allowed in return statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset SEQUENTIAL_STATEMENTS
Language VHDL
Type Block-level
Severity Error

Concurrent Statements Ruleset

The following rules are from the concurrent statements ruleset:

SYN9_1_1

Message: Guard expressions not allowed in block statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_1_2_A

Message: Port block headers are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_1_2_B

Message: Generic block headers are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_1_3_A

Message: Alias declarations are ignored in block statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_1_3_B

Message: Disconnection specifications are ignored in block statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_1_3_C

Message: Group template declarations are not supported in block statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_1_3_D

Message: File declarations are not supported in block statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_1_3_E

Message: Configuration specifications are not supported in block statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_1_3_F

Message: Group declarations are not supported in block statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_1_3_G

Message: Shared variable declarations are not supported in block_statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_2_1

Message: Postponed processes are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_2_2_A

Message: Group template declarations are not supported in process statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_2_2_B

Message: Group declarations are not supported in process statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_2_2_C

Message: Alias declarations are ignored in process statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_2_2_D

Message: Use clauses in process statements can only refer to package declarations

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_2_2_E

Message: File declarations are not supported in process statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_2_3

Message: Variable is read first on at least one flow of control or is read without being initialized within the process body

Description Ensuring that a variable is always written before being read avoids memory inference.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_2_4

Message: Only one clock expression per process is allowed

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_3_1

Message: Postponed concurrent procedure calls are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_4_1

Message: Postponed concurrent assertion statements are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_4_2

Message: Concurrent assertion statements are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_1_1

Message: Postponed conditional signal assignments are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_5_1_2

Message: Illegal conditional waveform

Description Don't use "unaffected" or "after" clauses. Only one waveform element per conditional waveform is permitted. Also, no condition on the last conditional waveform is permitted.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_5_1_3_A

Message: Inertial keyword on conditional signal assignments is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_1_3_B

Message: Reject expressions on conditional signal assignments are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_1_3_C

Message: Transport keyword on conditional signal assignments is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_1_3_D

Message: Guarded keyword on conditional signal assignments is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_1_4

Message: Target signal cannot also be a source in conditional signal assignment

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_5_2_1

Message: Postponed selected signal assignments are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_5_2_2

Message: Illegal selected waveform

Description Don't use "unaffected" or "after" clauses.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_5_2_3_A

Message: Transport keyword on selected signal assignments is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_2_3_B

Message: Inertial keyword on selected signal assignments is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_2_3_C

Message: Reject expressions on selected signal assignments are ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_2_3_D

Message: Guarded keyword on selected signal assignments is ignored

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Warning

SYN9_5_2_4

Message: Target signal cannot also be a source in selected signal assignment

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_6_1

Message: Entity names are not supported in component instantiation statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_6_2

Message: Configuration names are not supported in component instantiation statements

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

SYN9_7_1

Message: Block declarative part in generate statement is not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset CONCURRENT_STATEMENTS
Language VHDL
Type Block-level
Severity Error

Lexical Elements Ruleset

The following rule is from the lexical elements ruleset:

SYN13_4_1

Message: Real literals are not allowed

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset LEXICAL_ELEMENTS
Language VHDL
Type Block-level
Severity Error

Language Environment Ruleset

The following rules are from the language environment ruleset:

SYN14_1_1

Message: Illegal attribute

Description Most synthesis tools only support the following predefined attributes: BASE, LEFT, RIGHT, LOW, HIGH, LENGTH, RANGE, REVERSE_RANGE, EVENT, STABLE.
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset LANGUAGE_ENVT
Language VHDL
Type Block-level
Severity Error

SYN14_3_1

Message: Functions in STD.TEXTIO are not supported

Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset LANGUAGE_ENVT
Language VHDL
Type Block-level
Severity Error