| Class | Date | Topic | Reading | Exercises |
| 1 | Aug. 26 | Introduction | Weste 1.1-4, notes | |
| 2 | Aug. 28 | CMOS Capabilities and Limitations |
Weste 1.5, 1.8, notes | |
| 3 | Sep. 2 |
CMOS Transistors and Logic | Weste 2.1, notes | Lab 1 |
| 4 | Sep. 4 |
CMOS Transistor Characteristics | Weste 2.2 | |
| 5 | Sep. 9 |
CMOS DC
Characteristics
A CMOS Inverter Analysis |
Weste 2.3, 2.6, 2.7 | Homework 1 |
| 6 | Sep. 11 | Noise Margins
CAD Tools: SPICE |
OrCAD manual, online tutorial | |
| 7 | Sep. 16 | PSPICE
CMOS Physical Models and Processes |
Class Notes Weste 3.1 | |
| 8 | Sep. 18 | Layer Abstraction CMOS Technology: layers |
Weste 3.2 | Lab 2 |
| 9 | Sep. 23 | Scalable CMOS; Process Enhancements | Weste 3.3.3 Weste 3.4 |
Homework 2 SPICE Simulations |
| 10 | Sep. 25 | Fabrication Video |
class web site | |
| 11 | Sep. 30 |
Design Rules and MOSIS | Weste 3.3 notes | Mask Generation |
| 12 | Oct. 2 |
CADENCE Layout Tools (lab demo); Design Rules |
MOSIS web site Weste 3.3 | |
| 13 | Oct. 7 | Latchup | Weste 4.8.5 | |
| 14 | Oct. 9 |
Sheet Resistance; Stray R, L, C | Weste 4.5 |
Layout Design #1 |
| 15 | Oct. 14 | Cap. calculation | Weste 4.5 | |
| 16 | Oct. 16 | Switching Characteristics - time domain | ||
| 17 | Oct. 21 | Midterm | Depending on class progress | |
| 18 | Oct. 23 | Transistor Sizing and Power Dissipation | Weste 4.4 | Layout Design #2 |
| 19 | Oct. 28 | Charge Sharing | notes | Layout Design #3 |
| 20 | Oct.. 30 |
Gate Sizing | notes | |
| 21 | Nov. 4 |
Transmission gates, flip-flops | ||
| 22 | Nov. 6 |
Design Style and Variations | ||
| 23 | Nov. 11 | Clocked CMOS Logic | ||
| 24 | Nov. 13 | I/O Structures | notes | |
| 25 | Nov. 18 | I/O Structures and Pad Design |
notes | |
| 26 | Nov. 20 | Project discussion; Clocking Strategies | ||
| --- | Nov. 22-30 | Thanksgiving Break | ||
| 27 | Dec. 2 |
Project discussion; Caltech Intermediate Form | notes | |
| 28 | Dec. 4 |
More Clocking Strategies; Scaling, Yield | Weste 4.9 | |
| 29 | Dec. 9 |
Low-Power Design Techniques; |
||
| -- | Dec. 10 | Project due date (11:55 PM) | ||
| -- | Dec. 16 | Final Exam - normal classroom 7:45 AM - 9:45 AM |
Comprehensive |